gpu: nvgpu: common: Fix MISRA 15.6 violations

This fixes errors due to single statement loop bodies
 without braces, which is part of Rule 15.6 of MISRA.
 This patch covers in gpu/nvgpu/common/

JIRA NVGPU-989

Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786207
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index 327f67d3..2dcadb48 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -358,8 +358,9 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu,
                 }
         }
 
-        for (i = 0; i < PMU_QUEUE_COUNT; i++)
+        for (i = 0; i < PMU_QUEUE_COUNT; i++) {
                 nvgpu_pmu_queue_init(pmu, i, init);
+        }
 
         if (!nvgpu_alloc_initialized(&pmu->dmem)) {
                 /* Align start and end addresses */
@@ -480,8 +481,9 @@ static int nvgpu_pg_init_task(void *arg)
 
         }
 
-        while (!nvgpu_thread_should_stop(&pg_init->state_task))
+        while (!nvgpu_thread_should_stop(&pg_init->state_task)) {
                 nvgpu_usleep_range(5000, 5100);
+        }
 
         nvgpu_log_fn(g, "thread exit");