summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/common/pmu/pmu.c
diff options
context:
space:
mode:
authorMahantesh Kumbar <mkumbar@nvidia.com>2018-07-11 05:30:45 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-31 04:25:41 -0400
commit2d454db04fcc0c03e05b4665831e5780240d79b8 (patch)
treec18fd4bc302ea68e57e1e1d95c0f253e800bc043 /drivers/gpu/nvgpu/common/pmu/pmu.c
parentd32692ae2427693daf85b3c7b4e24cd36471dec6 (diff)
gpu: nvgpu: falcon queue support
-Renamed "struct pmu_queue" to "struct nvgpu_falcon_queue" & moved to falcon.h -Renamed pmu_queue_* functions to flcn_queue_* & moved to new file falcon_queue.c -Created ops for queue functions in struct nvgpu_falcon_queue to support different queue types like DMEM/FB-Q. -Created ops in nvgpu_falcon_engine_dependency_ops to add engine specific queue functionality & assigned correct HAL functions in hal*.c file. -Made changes in dependent functions as needed to replace struct pmu_queue & calling queue functions using nvgpu_falcon_queue data structure. -Replaced input param "struct nvgpu_pmu *pmu" with "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail & also for functions gk20a_pmu_queue_head()/ gk20a_pmu_queue_tail(). -Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue for PMU queue. -Modified Makefile to include falcon_queue.o -Modified Makefile.sources to include falcon_queue.c Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776070 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/pmu/pmu.c')
-rw-r--r--drivers/gpu/nvgpu/common/pmu/pmu.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c
index b9ac50be..327f67d3 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu.c
@@ -517,8 +517,9 @@ int nvgpu_pmu_destroy(struct gk20a *g)
517 pmu->isr_enabled = false; 517 pmu->isr_enabled = false;
518 nvgpu_mutex_release(&pmu->isr_mutex); 518 nvgpu_mutex_release(&pmu->isr_mutex);
519 519
520 for (i = 0; i < PMU_QUEUE_COUNT; i++) 520 for (i = 0; i < PMU_QUEUE_COUNT; i++) {
521 nvgpu_mutex_destroy(&pmu->queue[i].mutex); 521 nvgpu_flcn_queue_free(pmu->flcn, &pmu->queue[i]);
522 }
522 523
523 nvgpu_pmu_state_change(g, PMU_STATE_OFF, false); 524 nvgpu_pmu_state_change(g, PMU_STATE_OFF, false);
524 pmu->pmu_ready = false; 525 pmu->pmu_ready = false;