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authorThomas Fleury <tfleury@nvidia.com>2018-04-16 19:52:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-09 16:25:18 -0400
commit703d00d730d230f9ac9970e7d2d22a7d8f0cd2d1 (patch)
tree2dec0fb4b51b79d0d6f4f1b19e9f3cbd71ba1d85 /drivers/gpu/nvgpu/common/nvlink.c
parentf9e55fbaf66c024125a19e1a773a1a4f0e9648f4 (diff)
gpu: nvgpu: nvlink endpoint ops to common code
Move nvlink endpoint operations to common code. These operations are invoked when handling nvlink core driver requests. Jira VQRM-3523 Change-Id: I93024bf88a8caa3765b33c1264dde452c1a85ee3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698686 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/nvlink.c')
-rw-r--r--drivers/gpu/nvgpu/common/nvlink.c505
1 files changed, 505 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/nvlink.c b/drivers/gpu/nvgpu/common/nvlink.c
new file mode 100644
index 00000000..25c1b10b
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/nvlink.c
@@ -0,0 +1,505 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <gk20a/gk20a.h>
18#include <nvgpu/nvlink.h>
19#include <nvgpu/enabled.h>
20
21#ifdef CONFIG_TEGRA_NVLINK
22/*
23 * WAR: use this function to find detault link, as only one is supported
24 * on the library for now
25 * Returns NVLINK_MAX_LINKS_SW on failure
26 */
27static u32 __nvgpu_nvlink_get_link(struct nvlink_device *ndev)
28{
29 u32 link_id;
30 struct gk20a *g = (struct gk20a *) ndev->priv;
31
32 if (!g)
33 return NVLINK_MAX_LINKS_SW;
34
35 /* Lets find the detected link */
36 if (g->nvlink.initialized_links)
37 link_id = ffs(g->nvlink.initialized_links) - 1;
38 else
39 return NVLINK_MAX_LINKS_SW;
40
41 if (g->nvlink.links[link_id].remote_info.is_connected)
42 return link_id;
43
44 return NVLINK_MAX_LINKS_SW;
45}
46
47static int nvgpu_nvlink_early_init(struct nvlink_device *ndev)
48{
49 struct gk20a *g = (struct gk20a *) ndev->priv;
50 int err;
51
52 /* For now master topology is the only one supported */
53 if (!ndev->is_master) {
54 nvgpu_log(g, gpu_dbg_info | gpu_dbg_nvlink,
55 "dGPU is not master of Nvlink link");
56 return -EINVAL;
57 }
58
59 err = g->ops.nvlink.early_init(g);
60 return err;
61}
62
63static int nvgpu_nvlink_link_early_init(struct nvlink_device *ndev)
64{
65 struct gk20a *g = (struct gk20a *) ndev->priv;
66 int err;
67 u32 link_id;
68
69 /*
70 * First check the topology and setup connectivity
71 * HACK: we are only enabling one link for now!!!
72 */
73 link_id = ffs(g->nvlink.discovered_links) - 1;
74 g->nvlink.links[link_id].remote_info.is_connected = true;
75 g->nvlink.links[link_id].remote_info.device_type =
76 nvgpu_nvlink_endp_tegra;
77 err = g->ops.nvlink.link_early_init(g, BIT(link_id));
78
79 if (err == 0) {
80 g->nvlink.links[link_id].priv = (void *) &(ndev->link);
81 ndev->link.priv = (void *) g;
82 }
83 return err;
84}
85
86static int nvgpu_nvlink_interface_init(struct nvlink_device *ndev)
87{
88 int err;
89 struct gk20a *g = (struct gk20a *) ndev->priv;
90
91 err = g->ops.nvlink.interface_init(g);
92 return err;
93}
94
95static int nvgpu_nvlink_shutdown(struct nvlink_device *ndev)
96{
97 int err;
98 struct gk20a *g = (struct gk20a *) ndev->priv;
99
100 err = g->ops.nvlink.shutdown(g);
101 return 0;
102}
103
104static int nvgpu_nvlink_reg_init(struct nvlink_device *ndev)
105{
106 struct gk20a *g = (struct gk20a *) ndev->priv;
107 int err;
108
109 err = g->ops.nvlink.reg_init(g);
110
111 return err;
112}
113
114static u32 nvgpu_nvlink_get_link_mode(struct nvlink_device *ndev)
115{
116 struct gk20a *g = (struct gk20a *) ndev->priv;
117 u32 link_id;
118 u32 mode;
119
120 link_id = __nvgpu_nvlink_get_link(ndev);
121 if (link_id == NVLINK_MAX_LINKS_SW)
122 return -EINVAL;
123
124 mode = g->ops.nvlink.link_get_mode(g, link_id);
125
126 switch (mode) {
127 case nvgpu_nvlink_link_off:
128 return NVLINK_LINK_OFF;
129 case nvgpu_nvlink_link_hs:
130 return NVLINK_LINK_HS;
131 case nvgpu_nvlink_link_safe:
132 return NVLINK_LINK_SAFE;
133 case nvgpu_nvlink_link_fault:
134 return NVLINK_LINK_FAULT;
135 case nvgpu_nvlink_link_rcvy_ac:
136 return NVLINK_LINK_RCVY_AC;
137 case nvgpu_nvlink_link_rcvy_sw:
138 return NVLINK_LINK_RCVY_SW;
139 case nvgpu_nvlink_link_rcvy_rx:
140 return NVLINK_LINK_RCVY_RX;
141 case nvgpu_nvlink_link_detect:
142 return NVLINK_LINK_DETECT;
143 case nvgpu_nvlink_link_reset:
144 return NVLINK_LINK_RESET;
145 case nvgpu_nvlink_link_enable_pm:
146 return NVLINK_LINK_ENABLE_PM;
147 case nvgpu_nvlink_link_disable_pm:
148 return NVLINK_LINK_DISABLE_PM;
149 case nvgpu_nvlink_link_disable_err_detect:
150 return NVLINK_LINK_DISABLE_ERR_DETECT;
151 case nvgpu_nvlink_link_lane_disable:
152 return NVLINK_LINK_LANE_DISABLE;
153 case nvgpu_nvlink_link_lane_shutdown:
154 return NVLINK_LINK_LANE_SHUTDOWN;
155 default:
156 nvgpu_log(g, gpu_dbg_info | gpu_dbg_nvlink,
157 "unsupported mode %u", mode);
158 }
159
160 return NVLINK_LINK_OFF;
161}
162
163static u32 nvgpu_nvlink_get_link_state(struct nvlink_device *ndev)
164{
165 struct gk20a *g = (struct gk20a *) ndev->priv;
166 u32 link_id;
167
168 link_id = __nvgpu_nvlink_get_link(ndev);
169 if (link_id == NVLINK_MAX_LINKS_SW)
170 return -EINVAL;
171
172 return g->ops.nvlink.link_get_state(g, link_id);
173}
174
175static int nvgpu_nvlink_set_link_mode(struct nvlink_device *ndev, u32 mode)
176{
177
178 struct gk20a *g = (struct gk20a *) ndev->priv;
179 u32 link_id;
180 u32 mode_sw;
181
182 link_id = __nvgpu_nvlink_get_link(ndev);
183 if (link_id == NVLINK_MAX_LINKS_SW)
184 return -EINVAL;
185
186 switch (mode) {
187 case NVLINK_LINK_OFF:
188 mode_sw = nvgpu_nvlink_link_off;
189 break;
190 case NVLINK_LINK_HS:
191 mode_sw = nvgpu_nvlink_link_hs;
192 break;
193 case NVLINK_LINK_SAFE:
194 mode_sw = nvgpu_nvlink_link_safe;
195 break;
196 case NVLINK_LINK_FAULT:
197 mode_sw = nvgpu_nvlink_link_fault;
198 break;
199 case NVLINK_LINK_RCVY_AC:
200 mode_sw = nvgpu_nvlink_link_rcvy_ac;
201 break;
202 case NVLINK_LINK_RCVY_SW:
203 mode_sw = nvgpu_nvlink_link_rcvy_sw;
204 break;
205 case NVLINK_LINK_RCVY_RX:
206 mode_sw = nvgpu_nvlink_link_rcvy_rx;
207 break;
208 case NVLINK_LINK_DETECT:
209 mode_sw = nvgpu_nvlink_link_detect;
210 break;
211 case NVLINK_LINK_RESET:
212 mode_sw = nvgpu_nvlink_link_reset;
213 break;
214 case NVLINK_LINK_ENABLE_PM:
215 mode_sw = nvgpu_nvlink_link_enable_pm;
216 break;
217 case NVLINK_LINK_DISABLE_PM:
218 mode_sw = nvgpu_nvlink_link_disable_pm;
219 break;
220 case NVLINK_LINK_LANE_DISABLE:
221 mode_sw = nvgpu_nvlink_link_lane_disable;
222 break;
223 case NVLINK_LINK_LANE_SHUTDOWN:
224 mode_sw = nvgpu_nvlink_link_lane_shutdown;
225 break;
226 default:
227 mode_sw = nvgpu_nvlink_link_off;
228 }
229
230 return g->ops.nvlink.link_set_mode(g, link_id, mode_sw);
231}
232
233static void nvgpu_nvlink_get_tx_sublink_state(struct nvlink_device *ndev, u32 *state)
234{
235 struct gk20a *g = (struct gk20a *) ndev->priv;
236 u32 link_id;
237
238 link_id = __nvgpu_nvlink_get_link(ndev);
239 if (link_id == NVLINK_MAX_LINKS_SW)
240 return;
241 if (state)
242 *state = g->ops.nvlink.get_tx_sublink_state(g, link_id);
243}
244
245static void nvgpu_nvlink_get_rx_sublink_state(struct nvlink_device *ndev, u32 *state)
246{
247 struct gk20a *g = (struct gk20a *) ndev->priv;
248 u32 link_id;
249
250 link_id = __nvgpu_nvlink_get_link(ndev);
251 if (link_id == NVLINK_MAX_LINKS_SW)
252 return;
253 if (state)
254 *state = g->ops.nvlink.get_rx_sublink_state(g, link_id);
255}
256
257static u32 nvgpu_nvlink_get_sublink_mode(struct nvlink_device *ndev,
258 bool is_rx_sublink)
259{
260 struct gk20a *g = (struct gk20a *) ndev->priv;
261 u32 link_id;
262 u32 mode;
263
264 link_id = __nvgpu_nvlink_get_link(ndev);
265 if (link_id == NVLINK_MAX_LINKS_SW)
266 return -EINVAL;
267
268 mode = g->ops.nvlink.get_sublink_mode(g, link_id, is_rx_sublink);
269
270 switch (mode) {
271 case nvgpu_nvlink_sublink_tx_hs:
272 return NVLINK_TX_HS;
273 case nvgpu_nvlink_sublink_tx_off:
274 return NVLINK_TX_OFF;
275 case nvgpu_nvlink_sublink_tx_single_lane:
276 return NVLINK_TX_SINGLE_LANE;
277 case nvgpu_nvlink_sublink_tx_safe:
278 return NVLINK_TX_SAFE;
279 case nvgpu_nvlink_sublink_tx_enable_pm:
280 return NVLINK_TX_ENABLE_PM;
281 case nvgpu_nvlink_sublink_tx_disable_pm:
282 return NVLINK_TX_DISABLE_PM;
283 case nvgpu_nvlink_sublink_tx_common:
284 return NVLINK_TX_COMMON;
285 case nvgpu_nvlink_sublink_tx_common_disable:
286 return NVLINK_TX_COMMON_DISABLE;
287 case nvgpu_nvlink_sublink_tx_data_ready:
288 return NVLINK_TX_DATA_READY;
289 case nvgpu_nvlink_sublink_tx_prbs_en:
290 return NVLINK_TX_PRBS_EN;
291 case nvgpu_nvlink_sublink_rx_hs:
292 return NVLINK_RX_HS;
293 case nvgpu_nvlink_sublink_rx_enable_pm:
294 return NVLINK_RX_ENABLE_PM;
295 case nvgpu_nvlink_sublink_rx_disable_pm:
296 return NVLINK_RX_DISABLE_PM;
297 case nvgpu_nvlink_sublink_rx_single_lane:
298 return NVLINK_RX_SINGLE_LANE;
299 case nvgpu_nvlink_sublink_rx_safe:
300 return NVLINK_RX_SAFE;
301 case nvgpu_nvlink_sublink_rx_off:
302 return NVLINK_RX_OFF;
303 case nvgpu_nvlink_sublink_rx_rxcal:
304 return NVLINK_RX_RXCAL;
305 default:
306 nvgpu_log(g, gpu_dbg_nvlink, "Unsupported mode: %u", mode);
307 break;
308 }
309
310 if (is_rx_sublink)
311 return NVLINK_RX_OFF;
312 return NVLINK_TX_OFF;
313}
314
315static int nvgpu_nvlink_set_sublink_mode(struct nvlink_device *ndev,
316 bool is_rx_sublink, u32 mode)
317{
318 struct gk20a *g = (struct gk20a *) ndev->priv;
319 u32 link_id;
320 u32 mode_sw;
321
322 link_id = __nvgpu_nvlink_get_link(ndev);
323 if (link_id == NVLINK_MAX_LINKS_SW)
324 return -EINVAL;
325
326 if (!is_rx_sublink) {
327 switch (mode) {
328 case NVLINK_TX_HS:
329 mode_sw = nvgpu_nvlink_sublink_tx_hs;
330 break;
331 case NVLINK_TX_ENABLE_PM:
332 mode_sw = nvgpu_nvlink_sublink_tx_enable_pm;
333 break;
334 case NVLINK_TX_DISABLE_PM:
335 mode_sw = nvgpu_nvlink_sublink_tx_disable_pm;
336 break;
337 case NVLINK_TX_SINGLE_LANE:
338 mode_sw = nvgpu_nvlink_sublink_tx_single_lane;
339 break;
340 case NVLINK_TX_SAFE:
341 mode_sw = nvgpu_nvlink_sublink_tx_safe;
342 break;
343 case NVLINK_TX_OFF:
344 mode_sw = nvgpu_nvlink_sublink_tx_off;
345 break;
346 case NVLINK_TX_COMMON:
347 mode_sw = nvgpu_nvlink_sublink_tx_common;
348 break;
349 case NVLINK_TX_COMMON_DISABLE:
350 mode_sw = nvgpu_nvlink_sublink_tx_common_disable;
351 break;
352 case NVLINK_TX_DATA_READY:
353 mode_sw = nvgpu_nvlink_sublink_tx_data_ready;
354 break;
355 case NVLINK_TX_PRBS_EN:
356 mode_sw = nvgpu_nvlink_sublink_tx_prbs_en;
357 break;
358 default:
359 return -EINVAL;
360 }
361 } else {
362 switch (mode) {
363 case NVLINK_RX_HS:
364 mode_sw = nvgpu_nvlink_sublink_rx_hs;
365 break;
366 case NVLINK_RX_ENABLE_PM:
367 mode_sw = nvgpu_nvlink_sublink_rx_enable_pm;
368 break;
369 case NVLINK_RX_DISABLE_PM:
370 mode_sw = nvgpu_nvlink_sublink_rx_disable_pm;
371 break;
372 case NVLINK_RX_SINGLE_LANE:
373 mode_sw = nvgpu_nvlink_sublink_rx_single_lane;
374 break;
375 case NVLINK_RX_SAFE:
376 mode_sw = nvgpu_nvlink_sublink_rx_safe;
377 break;
378 case NVLINK_RX_OFF:
379 mode_sw = nvgpu_nvlink_sublink_rx_off;
380 break;
381 case NVLINK_RX_RXCAL:
382 mode_sw = nvgpu_nvlink_sublink_rx_rxcal;
383 break;
384 default:
385 return -EINVAL;
386 }
387 }
388
389 return g->ops.nvlink.set_sublink_mode(g, link_id, is_rx_sublink,
390 mode_sw);
391}
392
393static int nvgpu_nvlink_init_ops(struct gk20a *g)
394{
395 struct nvlink_device *ndev = g->nvlink.priv;
396
397 if (!ndev)
398 return -EINVAL;
399
400 /* Fill in device struct */
401 ndev->dev_ops.dev_early_init = nvgpu_nvlink_early_init;
402 ndev->dev_ops.dev_interface_init = nvgpu_nvlink_interface_init;
403 ndev->dev_ops.dev_reg_init = nvgpu_nvlink_reg_init;
404 ndev->dev_ops.dev_shutdown = nvgpu_nvlink_shutdown;
405
406 /* Fill in the link struct */
407 ndev->link.device_id = ndev->device_id;
408 ndev->link.mode = NVLINK_LINK_OFF;
409 ndev->link.link_ops.get_link_mode = nvgpu_nvlink_get_link_mode;
410 ndev->link.link_ops.set_link_mode = nvgpu_nvlink_set_link_mode;
411 ndev->link.link_ops.get_sublink_mode = nvgpu_nvlink_get_sublink_mode;
412 ndev->link.link_ops.set_sublink_mode = nvgpu_nvlink_set_sublink_mode;
413 ndev->link.link_ops.get_link_state = nvgpu_nvlink_get_link_state;
414 ndev->link.link_ops.get_tx_sublink_state =
415 nvgpu_nvlink_get_tx_sublink_state;
416 ndev->link.link_ops.get_rx_sublink_state =
417 nvgpu_nvlink_get_rx_sublink_state;
418 ndev->link.link_ops.link_early_init =
419 nvgpu_nvlink_link_early_init;
420
421 return 0;
422}
423
424int nvgpu_nvlink_enumerate(struct gk20a *g)
425{
426 struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
427
428 if (!ndev)
429 return -ENODEV;
430
431 return nvlink_enumerate(ndev);
432}
433
434int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off)
435{
436 struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
437
438 if (!ndev)
439 return -ENODEV;
440
441 /* Check if the link is connected */
442 if (!g->nvlink.links[link_id].remote_info.is_connected)
443 return -ENODEV;
444
445 if (from_off)
446 return nvlink_transition_intranode_conn_off_to_safe(ndev);
447
448 return nvlink_train_intranode_conn_safe_to_hs(ndev);
449}
450
451#endif
452
453int nvgpu_nvlink_probe(struct gk20a *g)
454{
455#ifdef CONFIG_TEGRA_NVLINK
456 int err;
457 struct nvlink_device *ndev;
458
459 /* Allocating structures */
460 ndev = nvgpu_kzalloc(g, sizeof(struct nvlink_device));
461 if (!ndev) {
462 nvgpu_err(g, "OOM while allocating nvlink device struct");
463 return -ENOMEM;
464 }
465
466 ndev->priv = (void *) g;
467 g->nvlink.priv = (void *) ndev;
468
469 err = nvgpu_nvlink_read_dt_props(g);
470 if (err)
471 goto free_ndev;
472
473 err = nvgpu_nvlink_init_ops(g);
474 if (err)
475 goto free_ndev;
476
477 /* Register device with core driver*/
478 err = nvlink_register_device(ndev);
479 if (err) {
480 nvgpu_err(g, "failed on nvlink device registration");
481 goto free_ndev;
482 }
483
484 /* Register link with core driver */
485 err = nvlink_register_link(&ndev->link);
486 if (err) {
487 nvgpu_err(g, "failed on nvlink link registration");
488 goto unregister_ndev;
489 }
490
491 /* Enable NVLINK support */
492 __nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
493 return 0;
494
495unregister_ndev:
496 nvlink_unregister_device(ndev);
497
498free_ndev:
499 nvgpu_kfree(g, ndev);
500 g->nvlink.priv = NULL;
501 return err;
502#else
503 return -ENODEV;
504#endif
505}
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