diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2019-04-30 04:24:08 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-05-09 17:41:30 -0400 |
commit | c81cc032c48a1b25e095b17b77399166c9091ff3 (patch) | |
tree | ace7d238c55bbb5e96fb6fd74deb156f3c513bae /drivers/gpu/nvgpu/common/mm | |
parent | f495f52c70c6bd7b7a4e6897270e4696efa57d5c (diff) |
gpu: nvgpu: add cg and pg function
Add new power/clock gating functions that can be called by
other units.
New clock_gating functions will reside in cg.c under
common/power_features/cg unit.
New power gating functions will reside in pg.c under
common/power_features/pg unit.
Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.
Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.
JIRA NVGPU-2014
Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in
dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2108406
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/mm.c | 20 |
1 files changed, 4 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index c9aac4af..fc7a9ae4 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <nvgpu/pramin.h> | 30 | #include <nvgpu/pramin.h> |
31 | #include <nvgpu/enabled.h> | 31 | #include <nvgpu/enabled.h> |
32 | #include <nvgpu/gk20a.h> | 32 | #include <nvgpu/gk20a.h> |
33 | #include <nvgpu/power_features/cg.h> | ||
33 | 34 | ||
34 | /* | 35 | /* |
35 | * Attempt to find a reserved memory area to determine PTE size for the passed | 36 | * Attempt to find a reserved memory area to determine PTE size for the passed |
@@ -349,22 +350,9 @@ static int nvgpu_init_mm_reset_enable_hw(struct gk20a *g) | |||
349 | g->ops.mc.fb_reset(g); | 350 | g->ops.mc.fb_reset(g); |
350 | } | 351 | } |
351 | 352 | ||
352 | if (g->ops.clock_gating.slcg_fb_load_gating_prod) { | 353 | nvgpu_cg_slcg_fb_ltc_load_enable(g); |
353 | g->ops.clock_gating.slcg_fb_load_gating_prod(g, | 354 | |
354 | g->slcg_enabled); | 355 | nvgpu_cg_blcg_fb_ltc_load_enable(g); |
355 | } | ||
356 | if (g->ops.clock_gating.slcg_ltc_load_gating_prod) { | ||
357 | g->ops.clock_gating.slcg_ltc_load_gating_prod(g, | ||
358 | g->slcg_enabled); | ||
359 | } | ||
360 | if (g->ops.clock_gating.blcg_fb_load_gating_prod) { | ||
361 | g->ops.clock_gating.blcg_fb_load_gating_prod(g, | ||
362 | g->blcg_enabled); | ||
363 | } | ||
364 | if (g->ops.clock_gating.blcg_ltc_load_gating_prod) { | ||
365 | g->ops.clock_gating.blcg_ltc_load_gating_prod(g, | ||
366 | g->blcg_enabled); | ||
367 | } | ||
368 | 356 | ||
369 | if (g->ops.fb.init_fs_state) { | 357 | if (g->ops.fb.init_fs_state) { |
370 | g->ops.fb.init_fs_state(g); | 358 | g->ops.fb.init_fs_state(g); |