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authorseshendra Gadagottu <sgadagottu@nvidia.com>2018-06-14 15:41:03 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-06-25 13:54:56 -0400
commita012527dbde6308bc158d17cace96d2a2e9fdcfd (patch)
tree51004fc8133c4599829effe501b18dba3a92d910 /drivers/gpu/nvgpu/common/mm
parentcd6e821cf66837a2c3479e928414007064b9c496 (diff)
gpu: nvgpu: gv11b: fix fb flush issue
membar.sys does synchronization with the whole system (GPU and CPU), membar.gl does synchronization within the GPU. In gv11b, fb flush is generating membar.gl instead of membar.sys, which is an issue. To fix this issue. following WAR is used: 1. Use bar1 engine id and bind it to a particular pdb, 2. Then instead of a fb_flush, issue a tlb invalidate of the bar1 pdb. Now allocation of vm for bar1 instance block and bar1 binding is done without check for bar1 support. Only bar1 register mapping is done based on bar1 support enabled. Bug 2112790 Change-Id: I76f43f1178a68f10823d48bc9da55d2bd686dd52 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1750257 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm')
-rw-r--r--drivers/gpu/nvgpu/common/mm/mm.c15
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index c9b2b493..30e7351c 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -159,10 +159,8 @@ static void nvgpu_remove_mm_support(struct mm_gk20a *mm)
159 if (g->ops.mm.remove_bar2_vm) 159 if (g->ops.mm.remove_bar2_vm)
160 g->ops.mm.remove_bar2_vm(g); 160 g->ops.mm.remove_bar2_vm(g);
161 161
162 if (g->ops.mm.is_bar1_supported(g)) { 162 nvgpu_free_inst_block(g, &mm->bar1.inst_block);
163 nvgpu_free_inst_block(g, &mm->bar1.inst_block); 163 nvgpu_vm_put(mm->bar1.vm);
164 nvgpu_vm_put(mm->bar1.vm);
165 }
166 164
167 nvgpu_free_inst_block(g, &mm->pmu.inst_block); 165 nvgpu_free_inst_block(g, &mm->pmu.inst_block);
168 nvgpu_free_inst_block(g, &mm->hwpm.inst_block); 166 nvgpu_free_inst_block(g, &mm->hwpm.inst_block);
@@ -377,11 +375,10 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
377 if (err) 375 if (err)
378 return err; 376 return err;
379 377
380 if (g->ops.mm.is_bar1_supported(g)) { 378 err = nvgpu_init_bar1_vm(mm);
381 err = nvgpu_init_bar1_vm(mm); 379 if (err)
382 if (err) 380 return err;
383 return err; 381
384 }
385 if (g->ops.mm.init_bar2_vm) { 382 if (g->ops.mm.init_bar2_vm) {
386 err = g->ops.mm.init_bar2_vm(g); 383 err = g->ops.mm.init_bar2_vm(g);
387 if (err) 384 if (err)