diff options
author | Alex Waterman <alexw@nvidia.com> | 2018-07-20 14:12:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-21 18:44:02 -0400 |
commit | 652da8116966af2a8438a9a9f135a11b4e5c6c7b (patch) | |
tree | 550e66e9127bf44b03f44a0b9b4c39cbe5b42a14 /drivers/gpu/nvgpu/common/mm | |
parent | bcf83fab33d8f1821cfcfd8c03411ea2fcf5334b (diff) |
gpu: nvgpu: Force the PMU VM to use 128K large pages (gm20b)
Add a WAR for gm20b that allows us to force the PMU VM to use
128K large pages. For some reason setting the small page size
to 64K breaks the PMU boot. Unclear why. Bug needs to be filed
and fixed. Once fixed this patch can and should be reverted.
Bug 200105199
Change-Id: I2b4c9e214e2a6dff33bea18bd2359c33364ba03f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1782769
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/mm.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index 0608d66a..2e46e211 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c | |||
@@ -202,13 +202,21 @@ static int nvgpu_init_system_vm(struct mm_gk20a *mm) | |||
202 | struct gk20a *g = gk20a_from_mm(mm); | 202 | struct gk20a *g = gk20a_from_mm(mm); |
203 | struct nvgpu_mem *inst_block = &mm->pmu.inst_block; | 203 | struct nvgpu_mem *inst_block = &mm->pmu.inst_block; |
204 | u32 big_page_size = g->ops.mm.get_default_big_page_size(); | 204 | u32 big_page_size = g->ops.mm.get_default_big_page_size(); |
205 | u32 low_hole, aperture_size; | 205 | u64 low_hole, aperture_size; |
206 | |||
207 | /* | ||
208 | * For some reason the maxwell PMU code is dependent on the large page | ||
209 | * size. No reason AFAICT for this. Probably a bug somewhere. | ||
210 | */ | ||
211 | if (nvgpu_is_enabled(g, NVGPU_MM_FORCE_128K_PMU_VM)) { | ||
212 | big_page_size = SZ_128K; | ||
213 | } | ||
206 | 214 | ||
207 | /* | 215 | /* |
208 | * No user region - so we will pass that as zero sized. | 216 | * No user region - so we will pass that as zero sized. |
209 | */ | 217 | */ |
210 | low_hole = SZ_4K * 16; | 218 | low_hole = SZ_4K * 16UL; |
211 | aperture_size = GK20A_PMU_VA_SIZE * 2; | 219 | aperture_size = GK20A_PMU_VA_SIZE; |
212 | 220 | ||
213 | mm->pmu.aperture_size = GK20A_PMU_VA_SIZE; | 221 | mm->pmu.aperture_size = GK20A_PMU_VA_SIZE; |
214 | nvgpu_log_info(g, "pmu vm size = 0x%x", mm->pmu.aperture_size); | 222 | nvgpu_log_info(g, "pmu vm size = 0x%x", mm->pmu.aperture_size); |