summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/common/mm
diff options
context:
space:
mode:
authorAlex Waterman <alexw@nvidia.com>2017-07-06 20:22:03 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-07 10:05:40 -0400
commit57abaabb7688016feaecbf529a46ad143c1e65a2 (patch)
treeb0482a63aac13eb840d0344d7345b5b2ef3d3dd6 /drivers/gpu/nvgpu/common/mm
parent6065b8c3ac17497d6ed8382a8503f55ec07c8865 (diff)
gpu: nvgpu: Cleanup GMMU debug printing
Ensure that all debug prints are consistent from chip to chip and function to function. The following maps letters in the debug print to their meaning: C Mapping is cachable v Mapping is volatile S Mapping is sparse P Mapping is private (VPR/WPR) c Mapping is coherent V Mapping is valid JIRA NVGPU-30 Change-Id: Ia890af88677c3e6d3fdd8c4fe266158c35b8afcd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1514903 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm')
-rw-r--r--drivers/gpu/nvgpu/common/mm/gmmu.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index dcb53c2a..1f3519aa 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -666,7 +666,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
666 "vm=%s " 666 "vm=%s "
667 "%-5s GPU virt %#-12llx +%#-9llx phys %#-12llx " 667 "%-5s GPU virt %#-12llx +%#-9llx phys %#-12llx "
668 "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " 668 "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | "
669 "kind=%#02x APT=%-6s %c%c%c", 669 "kind=%#02x APT=%-6s %c%c%c%c%c",
670 vm->name, 670 vm->name,
671 sgt ? "MAP" : "UNMAP", 671 sgt ? "MAP" : "UNMAP",
672 virt_addr, 672 virt_addr,
@@ -677,9 +677,11 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
677 nvgpu_gmmu_perm_str(attrs->rw_flag), 677 nvgpu_gmmu_perm_str(attrs->rw_flag),
678 attrs->kind_v, 678 attrs->kind_v,
679 nvgpu_aperture_str(attrs->aperture), 679 nvgpu_aperture_str(attrs->aperture),
680 attrs->cacheable ? 'C' : 'V', /* C = cached, V = volatile. */ 680 attrs->cacheable ? 'C' : 'c', /* C = cached, V = volatile. */
681 attrs->sparse ? 'S' : '-', 681 attrs->sparse ? 'S' : '-',
682 attrs->priv ? 'P' : '-'); 682 attrs->priv ? 'P' : '-',
683 attrs->coherent ? 'c' : '-',
684 attrs->valid ? 'V' : '-');
683 685
684 /* 686 /*
685 * Handle VIDMEM progamming. Currently uses a different scatter list 687 * Handle VIDMEM progamming. Currently uses a different scatter list