gpu: nvgpu: common: fix MISRA Rule 10.4

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fix violations where an arithmetic operation is performed on
signed and unsigned int types.

In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.

JIRA NVGPU-992

Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

10 files changed, 70 insertions, 70 deletions

diff --git a/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c b/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c
index 5316783d..1edfda51 100644
--- a/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/bitmap_allocator.c
@@ -378,7 +378,7 @@ int nvgpu_bitmap_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
         int err;
         struct nvgpu_bitmap_allocator *a;
 
-        if (WARN_ON(blk_size & (blk_size - 1))) {
+        if (WARN_ON(blk_size & (blk_size - 1U))) {
                 return -EINVAL;
         }
 
@@ -386,12 +386,12 @@ int nvgpu_bitmap_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
          * blk_size must be a power-of-2; base length also need to be aligned
          * to blk_size.
          */
-        if (blk_size & (blk_size - 1) ||
-            base & (blk_size - 1) || length & (blk_size - 1)) {
+        if (blk_size & (blk_size - 1U) ||
+            base & (blk_size - 1U) || length & (blk_size - 1U)) {
                 return -EINVAL;
         }
 
-        if (base == 0) {
+        if (base == 0U) {
                 base = blk_size;
                 length -= blk_size;
         }
diff --git a/drivers/gpu/nvgpu/common/mm/buddy_allocator.c b/drivers/gpu/nvgpu/common/mm/buddy_allocator.c
index e684e637..a9f90069 100644
--- a/drivers/gpu/nvgpu/common/mm/buddy_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/buddy_allocator.c
@@ -74,7 +74,7 @@ static void balloc_compute_max_order(struct nvgpu_buddy_allocator *a)
 {
         u64 true_max_order = ilog2(a->blks);
 
-        if (a->max_order == 0) {
+        if (a->max_order == 0U) {
                 a->max_order = true_max_order;
                 return;
         }
@@ -95,7 +95,7 @@ static void balloc_allocator_align(struct nvgpu_buddy_allocator *a)
 {
         a->start = ALIGN(a->base, a->blk_size);
         WARN_ON(a->start != a->base);
-        a->end   = (a->base + a->length) & ~(a->blk_size - 1);
+        a->end   = (a->base + a->length) & ~(a->blk_size - 1U);
         a->count = a->end - a->start;
         a->blks  = a->count >> a->blk_shift;
 }
@@ -119,7 +119,7 @@ static struct nvgpu_buddy *balloc_new_buddy(struct nvgpu_buddy_allocator *a,
         new_buddy->parent = parent;
         new_buddy->start = start;
         new_buddy->order = order;
-        new_buddy->end = start + (1 << order) * a->blk_size;
+        new_buddy->end = start + (U64(1) << order) * a->blk_size;
         new_buddy->pte_size = BALLOC_PTE_SIZE_ANY;
 
         return new_buddy;
@@ -185,7 +185,7 @@ static void balloc_blist_rem(struct nvgpu_buddy_allocator *a,
 
 static u64 balloc_get_order(struct nvgpu_buddy_allocator *a, u64 len)
 {
-        if (len == 0) {
+        if (len == 0U) {
                 return 0;
         }
 
@@ -200,7 +200,7 @@ static u64 __balloc_max_order_in(struct nvgpu_buddy_allocator *a,
 {
         u64 size = (end - start) >> a->blk_shift;
 
-        if (size > 0) {
+        if (size > 0U) {
                 return min_t(u64, ilog2(size), a->max_order);
         } else {
                 return GPU_BALLOC_MAX_ORDER;
@@ -212,7 +212,7 @@ static u64 __balloc_max_order_in(struct nvgpu_buddy_allocator *a,
  */
 static int balloc_init_lists(struct nvgpu_buddy_allocator *a)
 {
-        int i;
+        u32 i;
         u64 bstart, bend, order;
         struct nvgpu_buddy *buddy;
 
@@ -220,7 +220,7 @@ static int balloc_init_lists(struct nvgpu_buddy_allocator *a)
         bend = a->end;
 
         /* First make sure the LLs are valid. */
-        for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
+        for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
                 nvgpu_init_list_node(balloc_get_order_list(a, i));
         }
 
@@ -239,7 +239,7 @@ static int balloc_init_lists(struct nvgpu_buddy_allocator *a)
         return 0;
 
 cleanup:
-        for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
+        for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
                 if (!nvgpu_list_empty(balloc_get_order_list(a, i))) {
                         buddy = nvgpu_list_first_entry(
                                         balloc_get_order_list(a, i),
@@ -257,7 +257,7 @@ cleanup:
  */
 static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
 {
-        int i;
+        u32 i;
         struct nvgpu_rbtree_node *node = NULL;
         struct nvgpu_buddy *bud;
         struct nvgpu_fixed_alloc *falloc;
@@ -299,8 +299,8 @@ static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
         /*
          * Now clean up the unallocated buddies.
          */
-        for (i = 0; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
-                BUG_ON(a->buddy_list_alloced[i] != 0);
+        for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
+                BUG_ON(a->buddy_list_alloced[i] != 0U);
 
                 while (!nvgpu_list_empty(balloc_get_order_list(a, i))) {
                         bud = nvgpu_list_first_entry(
@@ -310,19 +310,19 @@ static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
                         nvgpu_kmem_cache_free(a->buddy_cache, bud);
                 }
 
-                if (a->buddy_list_len[i] != 0) {
+                if (a->buddy_list_len[i] != 0U) {
                         nvgpu_info(na->g,
                                         "Excess buddies!!! (%d: %llu)",
                                 i, a->buddy_list_len[i]);
                         BUG();
                 }
-                if (a->buddy_list_split[i] != 0) {
+                if (a->buddy_list_split[i] != 0U) {
                         nvgpu_info(na->g,
                                         "Excess split nodes!!! (%d: %llu)",
                                 i, a->buddy_list_split[i]);
                         BUG();
                 }
-                if (a->buddy_list_alloced[i] != 0) {
+                if (a->buddy_list_alloced[i] != 0U) {
                         nvgpu_info(na->g,
                                         "Excess alloced nodes!!! (%d: %llu)",
                                 i, a->buddy_list_alloced[i]);
@@ -392,14 +392,14 @@ static int balloc_split_buddy(struct nvgpu_buddy_allocator *a,
         struct nvgpu_buddy *left, *right;
         u64 half;
 
-        left = balloc_new_buddy(a, b, b->start, b->order - 1);
+        left = balloc_new_buddy(a, b, b->start, b->order - 1U);
         if (!left) {
                 return -ENOMEM;
         }
 
-        half = (b->end - b->start) / 2;
+        half = (b->end - b->start) / 2U;
 
-        right = balloc_new_buddy(a, b, b->start + half, b->order - 1);
+        right = balloc_new_buddy(a, b, b->start + half, b->order - 1U);
         if (!right) {
                 nvgpu_kmem_cache_free(a->buddy_cache, left);
                 return -ENOMEM;
@@ -624,7 +624,7 @@ static void __balloc_get_parent_range(struct nvgpu_buddy_allocator *a,
         u64 shifted_base = balloc_base_shift(a, base);
 
         order++;
-        base_mask = ~((a->blk_size << order) - 1);
+        base_mask = ~((a->blk_size << order) - 1U);
 
         shifted_base &= base_mask;
 
@@ -720,7 +720,7 @@ static u64 __balloc_do_alloc_fixed(struct nvgpu_buddy_allocator *a,
         u64 align_order;
 
         shifted_base = balloc_base_shift(a, base);
-        if (shifted_base == 0) {
+        if (shifted_base == 0U) {
                 align_order = __fls(len >> a->blk_shift);
         } else {
                 align_order = min_t(u64,
@@ -871,11 +871,11 @@ static u64 __nvgpu_balloc_fixed_buddy(struct nvgpu_allocator *na,
         struct nvgpu_buddy_allocator *a = na->priv;
 
         /* If base isn't aligned to an order 0 block, fail. */
-        if (base & (a->blk_size - 1)) {
+        if (base & (a->blk_size - 1U)) {
                 goto fail;
         }
 
-        if (len == 0) {
+        if (len == 0U) {
                 goto fail;
         }
 
@@ -1255,10 +1255,10 @@ int __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
         struct nvgpu_buddy_allocator *a;
 
         /* blk_size must be greater than 0 and a power of 2. */
-        if (blk_size == 0) {
+        if (blk_size == 0U) {
                 return -EINVAL;
         }
-        if (blk_size & (blk_size - 1)) {
+        if (blk_size & (blk_size - 1U)) {
                 return -EINVAL;
         }
 
@@ -1291,7 +1291,7 @@ int __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
          * If base is 0 then modfy base to be the size of one block so that we
          * can return errors by returning addr == 0.
          */
-        if (a->base == 0) {
+        if (a->base == 0U) {
                 a->base = a->blk_size;
                 a->length -= a->blk_size;
         }
@@ -1308,8 +1308,8 @@ int __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
          * requirement is not necessary.
          */
         if (flags & GPU_ALLOC_GVA_SPACE && vm->big_pages &&
-            (base & ((vm->big_page_size << 10) - 1) ||
-             size & ((vm->big_page_size << 10) - 1))) {
+            (base & ((vm->big_page_size << 10) - 1U) ||
+             size & ((vm->big_page_size << 10) - 1U))) {
                 return -EINVAL;
         }
 
diff --git a/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h b/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
index c9e332a5..fe3926b9 100644
--- a/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
+++ b/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
@@ -159,7 +159,7 @@ struct nvgpu_buddy_allocator {
         /*
          * Impose an upper bound on the maximum order.
          */
-#define GPU_BALLOC_ORDER_LIST_LEN       (GPU_BALLOC_MAX_ORDER + 1)
+#define GPU_BALLOC_ORDER_LIST_LEN       (GPU_BALLOC_MAX_ORDER + 1U)
 
         struct nvgpu_list_node buddy_list[GPU_BALLOC_ORDER_LIST_LEN];
         u64 buddy_list_len[GPU_BALLOC_ORDER_LIST_LEN];
@@ -190,7 +190,7 @@ static inline struct nvgpu_buddy_allocator *buddy_allocator(
 }
 
 static inline struct nvgpu_list_node *balloc_get_order_list(
-        struct nvgpu_buddy_allocator *a, int order)
+        struct nvgpu_buddy_allocator *a, u64 order)
 {
         return &a->buddy_list[order];
 }
diff --git a/drivers/gpu/nvgpu/common/mm/comptags.c b/drivers/gpu/nvgpu/common/mm/comptags.c
index 0926e78e..e6c99702 100644
--- a/drivers/gpu/nvgpu/common/mm/comptags.c
+++ b/drivers/gpu/nvgpu/common/mm/comptags.c
@@ -37,7 +37,7 @@ int gk20a_comptaglines_alloc(struct gk20a_comptag_allocator *allocator,
                         0, len, 0);
         if (addr < allocator->size) {
                 /* number zero is reserved; bitmap base is 1 */
-                *offset = 1 + addr;
+                *offset = 1U + addr;
                 bitmap_set(allocator->bitmap, addr, len);
         } else {
                 err = -ENOMEM;
@@ -51,9 +51,9 @@ void gk20a_comptaglines_free(struct gk20a_comptag_allocator *allocator,
                              u32 offset, u32 len)
 {
         /* number zero is reserved; bitmap base is 1 */
-        u32 addr = offset - 1;
+        u32 addr = offset - 1U;
 
-        WARN_ON(offset == 0);
+        WARN_ON(offset == 0U);
         WARN_ON(addr > allocator->size);
         WARN_ON(addr + len > allocator->size);
 
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index 02273393..47d1e8ee 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -98,7 +98,7 @@ static u64 __nvgpu_gmmu_map(struct vm_gk20a *vm,
          * therefor we should not try and free it. But otherwise, if we do
          * manage the VA alloc, we obviously must free it.
          */
-        if (addr != 0) {
+        if (addr != 0U) {
                 mem->free_gpu_va = false;
         } else {
                 mem->free_gpu_va = true;
@@ -300,7 +300,7 @@ static int pd_allocate(struct vm_gk20a *vm,
 static u32 pd_index(const struct gk20a_mmu_level *l, u64 virt,
                     struct nvgpu_gmmu_attrs *attrs)
 {
-        u64 pd_mask = (1ULL << ((u64)l->hi_bit[attrs->pgsz] + 1)) - 1ULL;
+        u64 pd_mask = (1ULL << ((u64)l->hi_bit[attrs->pgsz] + 1U)) - 1ULL;
         u32 pd_shift = (u64)l->lo_bit[attrs->pgsz];
 
         /*
@@ -399,7 +399,7 @@ static int __set_pd_level(struct vm_gk20a *vm,
                  * start at a PDE boundary.
                  */
                 chunk_size = min(length,
-                                 pde_range - (virt_addr & (pde_range - 1)));
+                                 pde_range - (virt_addr & (pde_range - 1U)));
 
                 /*
                  * If the next level has an update_entry function then we know
@@ -573,7 +573,7 @@ static int __nvgpu_gmmu_do_update_page_table(struct vm_gk20a *vm,
                 virt_addr += chunk_length;
                 length    -= chunk_length;
 
-                if (length == 0) {
+                if (length == 0U) {
                         break;
                 }
         }
@@ -615,7 +615,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
 
         page_size = vm->gmmu_page_sizes[attrs->pgsz];
 
-        if (space_to_skip & (page_size - 1)) {
+        if (space_to_skip & (page_size - 1U)) {
                 return -EINVAL;
         }
 
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
index 345b947d..ab75b136 100644
--- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
@@ -205,15 +205,15 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
 
 u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
 {
-        WARN_ON(offset & 3);
+        WARN_ON(offset & 3U);
         return nvgpu_mem_rd32(g, mem, offset / sizeof(u32));
 }
 
 void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
                 u32 offset, void *dest, u32 size)
 {
-        WARN_ON(offset & 3);
-        WARN_ON(size & 3);
+        WARN_ON(offset & 3U);
+        WARN_ON(size & 3U);
 
         if (mem->aperture == APERTURE_SYSMEM) {
                 u8 *src = (u8 *)mem->cpu_va + offset;
@@ -246,15 +246,15 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
 
 void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data)
 {
-        WARN_ON(offset & 3);
+        WARN_ON(offset & 3U);
         nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data);
 }
 
 void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 void *src, u32 size)
 {
-        WARN_ON(offset & 3);
-        WARN_ON(size & 3);
+        WARN_ON(offset & 3U);
+        WARN_ON(size & 3U);
 
         if (mem->aperture == APERTURE_SYSMEM) {
                 u8 *dest = (u8 *)mem->cpu_va + offset;
@@ -274,11 +274,11 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 u32 c, u32 size)
 {
-        WARN_ON(offset & 3);
-        WARN_ON(size & 3);
-        WARN_ON(c & ~0xff);
+        WARN_ON(offset & 3U);
+        WARN_ON(size & 3U);
+        WARN_ON(c & ~0xffU);
 
-        c &= 0xff;
+        c &= 0xffU;
 
         if (mem->aperture == APERTURE_SYSMEM) {
                 u8 *dest = (u8 *)mem->cpu_va + offset;
diff --git a/drivers/gpu/nvgpu/common/mm/page_allocator.c b/drivers/gpu/nvgpu/common/mm/page_allocator.c
index f6d70435..3225f170 100644
--- a/drivers/gpu/nvgpu/common/mm/page_allocator.c
+++ b/drivers/gpu/nvgpu/common/mm/page_allocator.c
@@ -317,8 +317,8 @@ static void free_slab_page(struct nvgpu_page_allocator *a,
         palloc_dbg(a, "Freeing slab page @ 0x%012llx", slab_page->page_addr);
 
         BUG_ON((slab_page->state != SP_NONE && slab_page->state != SP_EMPTY) ||
-               slab_page->nr_objects_alloced != 0 ||
-               slab_page->bitmap != 0);
+               slab_page->nr_objects_alloced != 0U ||
+               slab_page->bitmap != 0U);
 
         nvgpu_free(&a->source_allocator, slab_page->page_addr);
         a->pages_freed++;
@@ -471,7 +471,7 @@ static void __nvgpu_free_slab(struct nvgpu_page_allocator *a,
 
         slab_page->nr_objects_alloced--;
 
-        if (slab_page->nr_objects_alloced == 0) {
+        if (slab_page->nr_objects_alloced == 0U) {
                 new_state = SP_EMPTY;
         } else {
                 new_state = SP_PARTIAL;
@@ -684,7 +684,7 @@ static u64 nvgpu_page_alloc(struct nvgpu_allocator *na, u64 len)
 
         alloc_lock(na);
         if (a->flags & GPU_ALLOC_4K_VIDMEM_PAGES &&
-            real_len <= (a->page_size / 2)) {
+            real_len <= (a->page_size / 2U)) {
                 alloc = __nvgpu_alloc_slab(a, real_len);
         } else {
                 alloc = __nvgpu_alloc_pages(a, real_len);
@@ -698,7 +698,7 @@ static u64 nvgpu_page_alloc(struct nvgpu_allocator *na, u64 len)
         __insert_page_alloc(a, alloc);
 
         a->nr_allocs++;
-        if (real_len > a->page_size / 2) {
+        if (real_len > a->page_size / 2U) {
                 a->pages_alloced += alloc->length >> a->page_shift;
         }
         alloc_unlock(na);
diff --git a/drivers/gpu/nvgpu/common/mm/pd_cache.c b/drivers/gpu/nvgpu/common/mm/pd_cache.c
index db48d168..335ef360 100644
--- a/drivers/gpu/nvgpu/common/mm/pd_cache.c
+++ b/drivers/gpu/nvgpu/common/mm/pd_cache.c
@@ -76,20 +76,20 @@
 
 static u32 nvgpu_pd_cache_nr(u32 bytes)
 {
-        return ilog2(bytes >> (NVGPU_PD_CACHE_MIN_SHIFT - 1));
+        return ilog2(bytes >> (NVGPU_PD_CACHE_MIN_SHIFT - 1U));
 }
 
 static u32 nvgpu_pd_cache_get_mask(struct nvgpu_pd_mem_entry *pentry)
 {
         u32 mask_offset = 1 << (PAGE_SIZE / pentry->pd_size);
 
-        return mask_offset - 1;
+        return mask_offset - 1U;
 }
 
 int nvgpu_pd_cache_init(struct gk20a *g)
 {
         struct nvgpu_pd_cache *cache;
-        int i;
+        u32 i;
 
         /*
          * This gets called from finalize_poweron() so we need to make sure we
@@ -105,7 +105,7 @@ int nvgpu_pd_cache_init(struct gk20a *g)
                 return -ENOMEM;
         }
 
-        for (i = 0; i < NVGPU_PD_CACHE_COUNT; i++) {
+        for (i = 0U; i < NVGPU_PD_CACHE_COUNT; i++) {
                 nvgpu_init_list_node(&cache->full[i]);
                 nvgpu_init_list_node(&cache->partial[i]);
         }
@@ -121,14 +121,14 @@ int nvgpu_pd_cache_init(struct gk20a *g)
 
 void nvgpu_pd_cache_fini(struct gk20a *g)
 {
-        int i;
+        u32 i;
         struct nvgpu_pd_cache *cache = g->mm.pd_cache;
 
         if (!cache) {
                 return;
         }
 
-        for (i = 0; i < NVGPU_PD_CACHE_COUNT; i++) {
+        for (i = 0U; i < NVGPU_PD_CACHE_COUNT; i++) {
                 WARN_ON(!nvgpu_list_empty(&cache->full[i]));
                 WARN_ON(!nvgpu_list_empty(&cache->partial[i]));
         }
@@ -305,7 +305,7 @@ static int nvgpu_pd_cache_alloc(struct gk20a *g, struct nvgpu_pd_cache *cache,
 
         pd_dbg(g, "PD-Alloc [C] %u bytes", bytes);
 
-        if (bytes & (bytes - 1) ||
+        if (bytes & (bytes - 1U) ||
             (bytes >= PAGE_SIZE ||
              bytes < NVGPU_PD_CACHE_MIN)) {
                 pd_dbg(g, "PD-Alloc [C]   Invalid (bytes=%u)!", bytes);
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c
index e556be12..b364f4d6 100644
--- a/drivers/gpu/nvgpu/common/mm/vm.c
+++ b/drivers/gpu/nvgpu/common/mm/vm.c
@@ -150,7 +150,7 @@ u64 __nvgpu_vm_alloc_va(struct vm_gk20a *vm, u64 size, u32 pgsz_idx)
         }
 
         /* Be certain we round up to page_size if needed */
-        size = (size + ((u64)page_size - 1)) & ~((u64)page_size - 1);
+        size = (size + ((u64)page_size - 1U)) & ~((u64)page_size - 1U);
 
         addr = nvgpu_alloc(vma, size);
         if (!addr) {
@@ -202,7 +202,7 @@ void nvgpu_vm_mapping_batch_finish(struct vm_gk20a *vm,
  */
 int nvgpu_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size)
 {
-        u64 mask = ((u64)vm->big_page_size << 10) - 1;
+        u64 mask = ((u64)vm->big_page_size << 10) - 1U;
 
         if (base & mask || size & mask) {
                 return 0;
@@ -252,7 +252,7 @@ static int nvgpu_init_sema_pool(struct vm_gk20a *vm)
         sema_sea->gpu_va = nvgpu_alloc_fixed(&vm->kernel,
                                              vm->va_limit -
                                              mm->channel.kernel_size,
-                                             512 * PAGE_SIZE,
+                                             512U * PAGE_SIZE,
                                              SZ_4K);
         if (!sema_sea->gpu_va) {
                 nvgpu_free(&vm->kernel, sema_sea->gpu_va);
@@ -296,7 +296,7 @@ int __nvgpu_vm_init(struct mm_gk20a *mm,
                 return -ENOMEM;
         }
 
-        if (WARN_ON(vm->guest_managed && kernel_reserved != 0)) {
+        if (WARN_ON(vm->guest_managed && kernel_reserved != 0U)) {
                 return -EINVAL;
         }
 
@@ -387,7 +387,7 @@ int __nvgpu_vm_init(struct mm_gk20a *mm,
         }
 
         kernel_vma_flags = (kernel_reserved + low_hole) == aperture_size ?
-                0 : GPU_ALLOC_GVA_SPACE;
+                0U : GPU_ALLOC_GVA_SPACE;
 
         /*
          * A "user" area only makes sense for the GVA spaces. For VMs where
@@ -967,7 +967,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
                                                 g, gk20a_cbc_op_clear,
                                                 comptags.offset,
                                                 (comptags.offset +
-                                                 comptags.lines - 1));
+                                                 comptags.lines - 1U));
                                         gk20a_comptags_finish_clear(
                                                 os_buf, err == 0);
                                         if (err) {
@@ -1036,7 +1036,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
                                       aperture);
 
         if (clear_ctags) {
-                gk20a_comptags_finish_clear(os_buf, map_addr != 0);
+                gk20a_comptags_finish_clear(os_buf, map_addr != 0U);
         }
 
         if (!map_addr) {
diff --git a/drivers/gpu/nvgpu/common/mm/vm_area.c b/drivers/gpu/nvgpu/common/mm/vm_area.c
index 7e2b5c34..c2c0d569 100644
--- a/drivers/gpu/nvgpu/common/mm/vm_area.c
+++ b/drivers/gpu/nvgpu/common/mm/vm_area.c
@@ -57,7 +57,7 @@ int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm,
                 return -EINVAL;
         }
 
-        if (map_addr & (vm->gmmu_page_sizes[pgsz_idx] - 1)) {
+        if (map_addr & (vm->gmmu_page_sizes[pgsz_idx] - 1U)) {
                 nvgpu_err(g, "map offset must be buffer page size aligned 0x%llx",
                           map_addr);
                 return -EINVAL;