gpu: nvgpu: common: fix MISRA Rule 10.4

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fix violations where an arithmetic operation is performed on
signed and unsigned int types.

In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.

JIRA NVGPU-992

Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 10 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
index 345b947d..ab75b136 100644
--- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
@@ -205,15 +205,15 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
 
 u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
 {
-        WARN_ON(offset & 3);
+        WARN_ON(offset & 3U);
         return nvgpu_mem_rd32(g, mem, offset / sizeof(u32));
 }
 
 void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
                 u32 offset, void *dest, u32 size)
 {
-        WARN_ON(offset & 3);
-        WARN_ON(size & 3);
+        WARN_ON(offset & 3U);
+        WARN_ON(size & 3U);
 
         if (mem->aperture == APERTURE_SYSMEM) {
                 u8 *src = (u8 *)mem->cpu_va + offset;
@@ -246,15 +246,15 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
 
 void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data)
 {
-        WARN_ON(offset & 3);
+        WARN_ON(offset & 3U);
         nvgpu_mem_wr32(g, mem, offset / sizeof(u32), data);
 }
 
 void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 void *src, u32 size)
 {
-        WARN_ON(offset & 3);
-        WARN_ON(size & 3);
+        WARN_ON(offset & 3U);
+        WARN_ON(size & 3U);
 
         if (mem->aperture == APERTURE_SYSMEM) {
                 u8 *dest = (u8 *)mem->cpu_va + offset;
@@ -274,11 +274,11 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 u32 c, u32 size)
 {
-        WARN_ON(offset & 3);
-        WARN_ON(size & 3);
-        WARN_ON(c & ~0xff);
+        WARN_ON(offset & 3U);
+        WARN_ON(size & 3U);
+        WARN_ON(c & ~0xffU);
 
-        c &= 0xff;
+        c &= 0xffU;
 
         if (mem->aperture == APERTURE_SYSMEM) {
                 u8 *dest = (u8 *)mem->cpu_va + offset;