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authorAlex Waterman <alexw@nvidia.com>2018-03-06 13:43:16 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-07 21:04:41 -0500
commit418f31cd91a5c3ca45f0920ed64205def49c8a80 (patch)
tree17e3e04065679788aeeff645842866df0d59ccd0 /drivers/gpu/nvgpu/common/mm/gmmu.c
parentf85a0d3e00b53453f3d5ca556f15465078473f31 (diff)
gpu: nvgpu: Enable IO coherency on GV100
This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434. This is a revert of a revert, etc, etc. It re-enables IO coherence again. JIRA EVLR-2333 Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1669722 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mm/gmmu.c')
-rw-r--r--drivers/gpu/nvgpu/common/mm/gmmu.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index e1942cbd..3b57e781 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -79,6 +79,13 @@ static u64 __nvgpu_gmmu_map(struct vm_gk20a *vm,
79 if (!sgt) 79 if (!sgt)
80 return -ENOMEM; 80 return -ENOMEM;
81 81
82 /*
83 * If the GPU is IO coherent and the DMA API is giving us IO coherent
84 * CPU mappings then we gotta make sure we use the IO coherent aperture.
85 */
86 if (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM))
87 flags |= NVGPU_VM_MAP_IO_COHERENT;
88
82 nvgpu_mutex_acquire(&vm->update_gmmu_lock); 89 nvgpu_mutex_acquire(&vm->update_gmmu_lock);
83 vaddr = g->ops.mm.gmmu_map(vm, addr, 90 vaddr = g->ops.mm.gmmu_map(vm, addr,
84 sgt, /* sg list */ 91 sgt, /* sg list */
@@ -627,7 +634,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
627 page_size >> 10, 634 page_size >> 10,
628 nvgpu_gmmu_perm_str(attrs->rw_flag), 635 nvgpu_gmmu_perm_str(attrs->rw_flag),
629 attrs->kind_v, 636 attrs->kind_v,
630 nvgpu_aperture_str(attrs->aperture), 637 nvgpu_aperture_str(g, attrs->aperture),
631 attrs->cacheable ? 'C' : '-', 638 attrs->cacheable ? 'C' : '-',
632 attrs->sparse ? 'S' : '-', 639 attrs->sparse ? 'S' : '-',
633 attrs->priv ? 'P' : '-', 640 attrs->priv ? 'P' : '-',
@@ -705,6 +712,13 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
705 attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC); 712 attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC);
706 713
707 /* 714 /*
715 * Handle the IO coherency aperture: make sure the .aperture field is
716 * correct based on the IO coherency flag.
717 */
718 if (attrs.coherent && attrs.aperture == APERTURE_SYSMEM)
719 attrs.aperture = __APERTURE_SYSMEM_COH;
720
721 /*
708 * Only allocate a new GPU VA range if we haven't already been passed a 722 * Only allocate a new GPU VA range if we haven't already been passed a
709 * GPU VA range. This facilitates fixed mappings. 723 * GPU VA range. This facilitates fixed mappings.
710 */ 724 */