gpu: nvgpu: Remove mm.get_iova_addr

Remove the mm.get_iova_addr() HAL and replace it with a new HAL
called mm.gpu_phys_addr(). This new HAL provides the real phys
address that should be passed to the GPU from a physical address
obtained from a scatter list. It also provides a mechanism by
which the HAL code can add extra bits to a GPU physical address
based on the attributes passed in. This is necessary during GMMU
page table programming.

Also remove the flags argument from the various address functions.
This flag was used for adding an IO coherence bit to the GPU
physical address which is not supported.

JIRA NVGPU-30

Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530864
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c
index 1be87c85..30be1b85 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu.c
@@ -201,7 +201,7 @@ u64 nvgpu_pde_phys_addr(struct gk20a *g, struct nvgpu_gmmu_pd *pd)
         if (g->mm.has_physical_mode)
                 page_addr = sg_phys(pd->mem->priv.sgt->sgl);
         else
-                page_addr = nvgpu_mem_get_base_addr(g, pd->mem, 0);
+                page_addr = nvgpu_mem_get_addr(g, pd->mem);
 
         return page_addr + pd->mem_offs;
 }
@@ -559,7 +559,7 @@ static int __nvgpu_gmmu_update_page_table_sysmem(struct vm_gk20a *vm,
         sgl = sgt->sgl;
 
         if (!g->mm.bypass_smmu) {
-                u64 io_addr = g->ops.mm.get_iova_addr(g, sgl, 0);
+                u64 io_addr = nvgpu_mem_get_addr_sgl(g, sgl);
 
                 io_addr += space_to_skip;
 
@@ -670,7 +670,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
 
                         phys_addr = alloc->base;
                 } else
-                        phys_addr = g->ops.mm.get_iova_addr(g, sgt->sgl, 0);
+                        phys_addr = nvgpu_mem_get_addr_sgl(g, sgt->sgl);
         }
 
         __gmmu_dbg(g, attrs,