gpu: nvgpu: Add MC APIs for reset masks

Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.

JIRA NVGPU-954

Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 88 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
index c4e682ec..1194be85 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
@@ -28,6 +28,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
 
 #include "mc_gm20b.h"
 
@@ -292,3 +293,51 @@ void gm20b_mc_log_pending_intrs(struct gk20a *g)
         }
 }
 
+u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
+{
+        u32 mask = 0;
+
+        switch(unit) {
+        case NVGPU_UNIT_FIFO:
+                mask = mc_enable_pfifo_enabled_f();
+                break;
+        case NVGPU_UNIT_PERFMON:
+                mask = mc_enable_perfmon_enabled_f();
+                break;
+        case NVGPU_UNIT_GRAPH:
+                mask = mc_enable_pgraph_enabled_f();
+                break;
+        case NVGPU_UNIT_BLG:
+                mask = mc_enable_blg_enabled_f();
+                break;
+        case NVGPU_UNIT_PWR:
+                mask = mc_enable_pwr_enabled_f();
+                break;
+        default:
+                nvgpu_err(g, "unknown reset unit %d", unit);
+                BUG();
+                break;
+        }
+
+        return mask;
+}
+
+bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
+{
+        u32 mask = g->ops.mc.reset_mask(g, unit);
+
+        return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
+}
+
+void gm20b_mc_fb_reset(struct gk20a *g)
+{
+        u32 val;
+
+        nvgpu_log_info(g, "reset gk20a fb");
+
+        val = gk20a_readl(g, mc_elpg_enable_r());
+        val |= mc_elpg_enable_xbar_enabled_f()
+                | mc_elpg_enable_pfb_enabled_f()
+                | mc_elpg_enable_hub_enabled_f();
+        gk20a_writel(g, mc_elpg_enable_r(), val);
+}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
index 6700a48c..fcf02077 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
+++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
@@ -47,5 +47,8 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g,
                 enum nvgpu_unit unit, u32 mc_intr_1);
 void gm20b_mc_log_pending_intrs(struct gk20a *g);
 void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops);
+u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
+bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
+void gm20b_mc_fb_reset(struct gk20a *g);
 
 #endif /* NVGPU_MC_GM20B_H */
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c
index b67f9bbe..77155d14 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gv100.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c
@@ -26,6 +26,8 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/unit.h>
+#include <nvgpu/bug.h>
 
 #include "mc_gp10b.h"
 #include "mc_gv100.h"
@@ -88,3 +90,35 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 
         return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
 }
+
+u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
+{
+        u32 mask = 0;
+
+        switch(unit) {
+        case NVGPU_UNIT_FIFO:
+                mask = mc_enable_pfifo_enabled_f();
+                break;
+        case NVGPU_UNIT_PERFMON:
+                mask = mc_enable_perfmon_enabled_f();
+                break;
+        case NVGPU_UNIT_GRAPH:
+                mask = mc_enable_pgraph_enabled_f();
+                break;
+        case NVGPU_UNIT_BLG:
+                mask = mc_enable_blg_enabled_f();
+                break;
+        case NVGPU_UNIT_PWR:
+                mask = mc_enable_pwr_enabled_f();
+                break;
+        case NVGPU_UNIT_NVDEC:
+                mask = mc_enable_nvdec_enabled_f();
+                break;
+        default:
+                nvgpu_err(g, "unknown reset unit %d", unit);
+                BUG();
+                break;
+        }
+
+        return mask;
+}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h
index c0a16ad9..764d59b1 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gv100.h
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h
@@ -31,4 +31,6 @@ void mc_gv100_intr_enable(struct gk20a *g);
 bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
 bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
                         u32 *eng_intr_pending);
+u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
+
 #endif