diff options
author | Seema Khowala <seemaj@nvidia.com> | 2019-01-31 18:35:59 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-02-02 06:51:02 -0500 |
commit | bcac2a22a40e5920e4d88b6dc849f37d55553d02 (patch) | |
tree | e54c62c8e6716f9c76a79ccb5d29cb26f23c78a6 /drivers/gpu/nvgpu/common/mc | |
parent | d39781054f63a510b0eaccee5e1099d7ae6ce132 (diff) |
gpu: nvgpu: gm20b: clear priv intr in log_pending_intrs
Clear pending priv interrupt in log_pending_intrs. Priv
ring errors have not been cleaned up in gm20b. It is ok
to just clear it.
Bug 200477291
Bug 200486293
Change-Id: I850a261828a9d49b6b4a82d75f5347acbc17b0fe
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008818
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc')
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index 1194be85..c33b4697 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Master Control | 2 | * GM20B Master Control |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -280,16 +280,24 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g, | |||
280 | 280 | ||
281 | void gm20b_mc_log_pending_intrs(struct gk20a *g) | 281 | void gm20b_mc_log_pending_intrs(struct gk20a *g) |
282 | { | 282 | { |
283 | u32 intr; | 283 | u32 mc_intr_0; |
284 | u32 mc_intr_1; | ||
284 | 285 | ||
285 | intr = g->ops.mc.intr_stall(g); | 286 | mc_intr_0 = g->ops.mc.intr_stall(g); |
286 | if (intr != 0U) { | 287 | if (mc_intr_0 != 0U) { |
287 | nvgpu_info(g, "Pending stall intr0=0x%08x", intr); | 288 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { |
289 | /* clear priv ring interrupts */ | ||
290 | g->ops.priv_ring.isr(g); | ||
291 | } | ||
292 | mc_intr_0 = g->ops.mc.intr_stall(g); | ||
293 | if (mc_intr_0 != 0U) { | ||
294 | nvgpu_info(g, "Pending stall intr0=0x%08x", mc_intr_0); | ||
295 | } | ||
288 | } | 296 | } |
289 | 297 | ||
290 | intr = g->ops.mc.intr_nonstall(g); | 298 | mc_intr_1 = g->ops.mc.intr_nonstall(g); |
291 | if (intr != 0U) { | 299 | if (mc_intr_1 != 0U) { |
292 | nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr); | 300 | nvgpu_info(g, "Pending nonstall intr1=0x%08x", mc_intr_1); |
293 | } | 301 | } |
294 | } | 302 | } |
295 | 303 | ||