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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-09-12 17:51:40 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-27 18:05:25 -0400
commite3ae03e17abd452c157545234348692364b4b9f6 (patch)
tree121b3dcde56c87f9a1008ad4f5effbeb69cff945 /drivers/gpu/nvgpu/common/mc/mc_gm20b.h
parent78e3d22da3c2513d425c8c2560468ce854a982dd (diff)
gpu: nvgpu: Add MC APIs for reset masks
Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc/mc_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/common/mc/mc_gm20b.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
index 6700a48c..fcf02077 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
+++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
@@ -47,5 +47,8 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g,
47 enum nvgpu_unit unit, u32 mc_intr_1); 47 enum nvgpu_unit unit, u32 mc_intr_1);
48void gm20b_mc_log_pending_intrs(struct gk20a *g); 48void gm20b_mc_log_pending_intrs(struct gk20a *g);
49void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); 49void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops);
50u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
51bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
52void gm20b_mc_fb_reset(struct gk20a *g);
50 53
51#endif /* NVGPU_MC_GM20B_H */ 54#endif /* NVGPU_MC_GM20B_H */