diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-09-12 17:51:40 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 18:05:25 -0400 |
commit | e3ae03e17abd452c157545234348692364b4b9f6 (patch) | |
tree | 121b3dcde56c87f9a1008ad4f5effbeb69cff945 /drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |
parent | 78e3d22da3c2513d425c8c2560468ce854a982dd (diff) |
gpu: nvgpu: Add MC APIs for reset masks
Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.
JIRA NVGPU-954
Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc/mc_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index c4e682ec..1194be85 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/io.h> | 28 | #include <nvgpu/io.h> |
29 | #include <nvgpu/mc.h> | 29 | #include <nvgpu/mc.h> |
30 | #include <nvgpu/gk20a.h> | 30 | #include <nvgpu/gk20a.h> |
31 | #include <nvgpu/bug.h> | ||
31 | 32 | ||
32 | #include "mc_gm20b.h" | 33 | #include "mc_gm20b.h" |
33 | 34 | ||
@@ -292,3 +293,51 @@ void gm20b_mc_log_pending_intrs(struct gk20a *g) | |||
292 | } | 293 | } |
293 | } | 294 | } |
294 | 295 | ||
296 | u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) | ||
297 | { | ||
298 | u32 mask = 0; | ||
299 | |||
300 | switch(unit) { | ||
301 | case NVGPU_UNIT_FIFO: | ||
302 | mask = mc_enable_pfifo_enabled_f(); | ||
303 | break; | ||
304 | case NVGPU_UNIT_PERFMON: | ||
305 | mask = mc_enable_perfmon_enabled_f(); | ||
306 | break; | ||
307 | case NVGPU_UNIT_GRAPH: | ||
308 | mask = mc_enable_pgraph_enabled_f(); | ||
309 | break; | ||
310 | case NVGPU_UNIT_BLG: | ||
311 | mask = mc_enable_blg_enabled_f(); | ||
312 | break; | ||
313 | case NVGPU_UNIT_PWR: | ||
314 | mask = mc_enable_pwr_enabled_f(); | ||
315 | break; | ||
316 | default: | ||
317 | nvgpu_err(g, "unknown reset unit %d", unit); | ||
318 | BUG(); | ||
319 | break; | ||
320 | } | ||
321 | |||
322 | return mask; | ||
323 | } | ||
324 | |||
325 | bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit) | ||
326 | { | ||
327 | u32 mask = g->ops.mc.reset_mask(g, unit); | ||
328 | |||
329 | return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U; | ||
330 | } | ||
331 | |||
332 | void gm20b_mc_fb_reset(struct gk20a *g) | ||
333 | { | ||
334 | u32 val; | ||
335 | |||
336 | nvgpu_log_info(g, "reset gk20a fb"); | ||
337 | |||
338 | val = gk20a_readl(g, mc_elpg_enable_r()); | ||
339 | val |= mc_elpg_enable_xbar_enabled_f() | ||
340 | | mc_elpg_enable_pfb_enabled_f() | ||
341 | | mc_elpg_enable_hub_enabled_f(); | ||
342 | gk20a_writel(g, mc_elpg_enable_r(), val); | ||
343 | } | ||