diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-08-30 17:05:16 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-13 22:18:24 -0400 |
commit | 7ac0b046a538daa1a3532d3d5ae7cba1ef3295ba (patch) | |
tree | 79e42a4abe1e0c7d2918fa588f50061b90ee3e5f /drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |
parent | bf14c2a0faf922073eaf72d490bf8bde8df1a5c7 (diff) |
gpu: nvgpu: Move MC HAL to common
Move implementation of MC HAL to common/mc. Also bump gk20a
implementation to gm20b.
gk20a_mc_boot_0 was used via a HAL, but we have only one possible
implementation. It also has to be anyway called directly to detect
which HALs to assign, so make it a true common function.
mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c
so move it there.
JIRA NVGPU-954
Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813519
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc/mc_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 294 |
1 files changed, 294 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c new file mode 100644 index 00000000..88666b1d --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -0,0 +1,294 @@ | |||
1 | /* | ||
2 | * GK20A Master Control | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/timers.h> | ||
26 | #include <nvgpu/atomic.h> | ||
27 | #include <nvgpu/unit.h> | ||
28 | #include <nvgpu/io.h> | ||
29 | #include <nvgpu/mc.h> | ||
30 | |||
31 | #include "gk20a/gk20a.h" | ||
32 | #include "mc_gm20b.h" | ||
33 | |||
34 | #include <nvgpu/hw/gm20b/hw_mc_gm20b.h> | ||
35 | |||
36 | void gm20b_mc_isr_stall(struct gk20a *g) | ||
37 | { | ||
38 | u32 mc_intr_0; | ||
39 | u32 engine_id_idx; | ||
40 | u32 active_engine_id = 0; | ||
41 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
42 | |||
43 | mc_intr_0 = g->ops.mc.intr_stall(g); | ||
44 | |||
45 | nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | ||
46 | |||
47 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | ||
48 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
49 | |||
50 | if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { | ||
51 | engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; | ||
52 | /* GR Engine */ | ||
53 | if (engine_enum == ENGINE_GR_GK20A) { | ||
54 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | ||
55 | } | ||
56 | |||
57 | /* CE Engine */ | ||
58 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
59 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
60 | (g->ops.ce2.isr_stall != NULL)) { | ||
61 | g->ops.ce2.isr_stall(g, | ||
62 | g->fifo.engine_info[active_engine_id].inst_id, | ||
63 | g->fifo.engine_info[active_engine_id].pri_base); | ||
64 | } | ||
65 | } | ||
66 | } | ||
67 | if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { | ||
68 | gk20a_fifo_isr(g); | ||
69 | } | ||
70 | if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { | ||
71 | g->ops.pmu.pmu_isr(g); | ||
72 | } | ||
73 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { | ||
74 | g->ops.priv_ring.isr(g); | ||
75 | } | ||
76 | if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { | ||
77 | g->ops.ltc.isr(g); | ||
78 | } | ||
79 | if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { | ||
80 | g->ops.bus.isr(g); | ||
81 | } | ||
82 | } | ||
83 | |||
84 | u32 gm20b_mc_isr_nonstall(struct gk20a *g) | ||
85 | { | ||
86 | u32 ops = 0; | ||
87 | u32 mc_intr_1; | ||
88 | u32 engine_id_idx; | ||
89 | u32 active_engine_id = 0; | ||
90 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
91 | |||
92 | mc_intr_1 = g->ops.mc.intr_nonstall(g); | ||
93 | |||
94 | if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1) != 0U) { | ||
95 | ops |= gk20a_fifo_nonstall_isr(g); | ||
96 | } | ||
97 | |||
98 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; | ||
99 | engine_id_idx++) { | ||
100 | struct fifo_engine_info_gk20a *engine_info; | ||
101 | |||
102 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
103 | engine_info = &g->fifo.engine_info[active_engine_id]; | ||
104 | |||
105 | if ((mc_intr_1 & engine_info->intr_mask) != 0U) { | ||
106 | engine_enum = engine_info->engine_enum; | ||
107 | /* GR Engine */ | ||
108 | if (engine_enum == ENGINE_GR_GK20A) { | ||
109 | ops |= gk20a_gr_nonstall_isr(g); | ||
110 | } | ||
111 | /* CE Engine */ | ||
112 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
113 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
114 | (g->ops.ce2.isr_nonstall != NULL)) { | ||
115 | ops |= g->ops.ce2.isr_nonstall(g, | ||
116 | engine_info->inst_id, | ||
117 | engine_info->pri_base); | ||
118 | } | ||
119 | } | ||
120 | } | ||
121 | |||
122 | return ops; | ||
123 | } | ||
124 | |||
125 | void gm20b_mc_intr_mask(struct gk20a *g) | ||
126 | { | ||
127 | nvgpu_writel(g, mc_intr_en_0_r(), | ||
128 | mc_intr_en_0_inta_disabled_f()); | ||
129 | nvgpu_writel(g, mc_intr_en_1_r(), | ||
130 | mc_intr_en_1_inta_disabled_f()); | ||
131 | } | ||
132 | |||
133 | void gm20b_mc_intr_enable(struct gk20a *g) | ||
134 | { | ||
135 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
136 | |||
137 | gk20a_writel(g, mc_intr_mask_1_r(), | ||
138 | mc_intr_pfifo_pending_f() | ||
139 | | eng_intr_mask); | ||
140 | gk20a_writel(g, mc_intr_en_1_r(), | ||
141 | mc_intr_en_1_inta_hardware_f()); | ||
142 | |||
143 | gk20a_writel(g, mc_intr_mask_0_r(), | ||
144 | mc_intr_pfifo_pending_f() | ||
145 | | mc_intr_priv_ring_pending_f() | ||
146 | | mc_intr_ltc_pending_f() | ||
147 | | mc_intr_pbus_pending_f() | ||
148 | | eng_intr_mask); | ||
149 | gk20a_writel(g, mc_intr_en_0_r(), | ||
150 | mc_intr_en_0_inta_hardware_f()); | ||
151 | } | ||
152 | |||
153 | void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, | ||
154 | bool is_stalling, u32 mask) | ||
155 | { | ||
156 | u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : | ||
157 | mc_intr_mask_1_r()); | ||
158 | |||
159 | if (enable) { | ||
160 | gk20a_writel(g, mask_reg, | ||
161 | gk20a_readl(g, mask_reg) | | ||
162 | mask); | ||
163 | } else { | ||
164 | gk20a_writel(g, mask_reg, | ||
165 | gk20a_readl(g, mask_reg) & | ||
166 | ~mask); | ||
167 | } | ||
168 | } | ||
169 | |||
170 | void gm20b_mc_intr_stall_pause(struct gk20a *g) | ||
171 | { | ||
172 | gk20a_writel(g, mc_intr_en_0_r(), | ||
173 | mc_intr_en_0_inta_disabled_f()); | ||
174 | |||
175 | /* flush previous write */ | ||
176 | (void) gk20a_readl(g, mc_intr_en_0_r()); | ||
177 | } | ||
178 | |||
179 | void gm20b_mc_intr_stall_resume(struct gk20a *g) | ||
180 | { | ||
181 | gk20a_writel(g, mc_intr_en_0_r(), | ||
182 | mc_intr_en_0_inta_hardware_f()); | ||
183 | |||
184 | /* flush previous write */ | ||
185 | (void) gk20a_readl(g, mc_intr_en_0_r()); | ||
186 | } | ||
187 | |||
188 | void gm20b_mc_intr_nonstall_pause(struct gk20a *g) | ||
189 | { | ||
190 | gk20a_writel(g, mc_intr_en_1_r(), | ||
191 | mc_intr_en_0_inta_disabled_f()); | ||
192 | |||
193 | /* flush previous write */ | ||
194 | (void) gk20a_readl(g, mc_intr_en_1_r()); | ||
195 | } | ||
196 | |||
197 | void gm20b_mc_intr_nonstall_resume(struct gk20a *g) | ||
198 | { | ||
199 | gk20a_writel(g, mc_intr_en_1_r(), | ||
200 | mc_intr_en_0_inta_hardware_f()); | ||
201 | |||
202 | /* flush previous write */ | ||
203 | (void) gk20a_readl(g, mc_intr_en_1_r()); | ||
204 | } | ||
205 | |||
206 | u32 gm20b_mc_intr_stall(struct gk20a *g) | ||
207 | { | ||
208 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); | ||
209 | } | ||
210 | |||
211 | u32 gm20b_mc_intr_nonstall(struct gk20a *g) | ||
212 | { | ||
213 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); | ||
214 | } | ||
215 | |||
216 | void gm20b_mc_disable(struct gk20a *g, u32 units) | ||
217 | { | ||
218 | u32 pmc; | ||
219 | |||
220 | nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units); | ||
221 | |||
222 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
223 | pmc = gk20a_readl(g, mc_enable_r()); | ||
224 | pmc &= ~units; | ||
225 | gk20a_writel(g, mc_enable_r(), pmc); | ||
226 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
227 | } | ||
228 | |||
229 | void gm20b_mc_enable(struct gk20a *g, u32 units) | ||
230 | { | ||
231 | u32 pmc; | ||
232 | |||
233 | nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units); | ||
234 | |||
235 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
236 | pmc = gk20a_readl(g, mc_enable_r()); | ||
237 | pmc |= units; | ||
238 | gk20a_writel(g, mc_enable_r(), pmc); | ||
239 | pmc = gk20a_readl(g, mc_enable_r()); | ||
240 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
241 | |||
242 | nvgpu_udelay(20); | ||
243 | } | ||
244 | |||
245 | void gm20b_mc_reset(struct gk20a *g, u32 units) | ||
246 | { | ||
247 | g->ops.mc.disable(g, units); | ||
248 | if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) { | ||
249 | nvgpu_udelay(500); | ||
250 | } else { | ||
251 | nvgpu_udelay(20); | ||
252 | } | ||
253 | g->ops.mc.enable(g, units); | ||
254 | } | ||
255 | |||
256 | bool gm20b_mc_is_intr1_pending(struct gk20a *g, | ||
257 | enum nvgpu_unit unit, u32 mc_intr_1) | ||
258 | { | ||
259 | u32 mask = 0U; | ||
260 | bool is_pending; | ||
261 | |||
262 | switch (unit) { | ||
263 | case NVGPU_UNIT_FIFO: | ||
264 | mask = mc_intr_pfifo_pending_f(); | ||
265 | break; | ||
266 | default: | ||
267 | break; | ||
268 | } | ||
269 | |||
270 | if (mask == 0U) { | ||
271 | nvgpu_err(g, "unknown unit %d", unit); | ||
272 | is_pending = false; | ||
273 | } else { | ||
274 | is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; | ||
275 | } | ||
276 | |||
277 | return is_pending; | ||
278 | } | ||
279 | |||
280 | void gm20b_mc_log_pending_intrs(struct gk20a *g) | ||
281 | { | ||
282 | u32 intr; | ||
283 | |||
284 | intr = g->ops.mc.intr_stall(g); | ||
285 | if (intr != 0U) { | ||
286 | nvgpu_info(g, "Pending stall intr0=0x%08x", intr); | ||
287 | } | ||
288 | |||
289 | intr = g->ops.mc.intr_nonstall(g); | ||
290 | if (intr != 0U) { | ||
291 | nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr); | ||
292 | } | ||
293 | } | ||
294 | |||