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author | Divya Singhatwaria <dsinghatwari@nvidia.com> | 2021-01-27 11:05:32 -0500 |
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committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2021-03-17 12:54:54 -0400 |
commit | 9170f2b77cba9aedd957acdde7c758e81e073cc0 (patch) | |
tree | 661d7acd1c425b7e5601e5b18d394fa9bd10a016 /drivers/gpu/nvgpu/common/ltc | |
parent | 7882f15ff63199a517852760f5686ecd0b886123 (diff) |
gpu: nvgpu: remove ZBC save/restore by PMU
- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
for GP10B
- Updated the GP10B PMU app version for the ucode:
https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260
P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520
Bug 3233071
Bug 200696431
Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476259
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/common/ltc')
0 files changed, 0 insertions, 0 deletions