diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-11-16 14:29:11 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-16 18:55:52 -0500 |
commit | b7cc3a2aa6c92a09eed43513287c9062f22ad127 (patch) | |
tree | 0943ccb3962312810ab236d98fb5ff09b8843119 /drivers/gpu/nvgpu/common/linux | |
parent | 3590080109511b203e9a9187f83aef61513d3d1a (diff) |
gpu: nvgpu: Fix some barrier usage
Commit 81868a187fa3b217368206f17b19309846e8e7fb updated barrier
usage to use the nvgpu wrappers and in doing so downgraded many
plain barriers {mb(), wmb(), rmb()} to the SMP versions of these
barriers.
The SMP version of the barriers in question are only issued
when running on an SMP machine. In most of the cases mentioned
above this is fine since the barriers are present to faciliate
proper ordering across CPUs. A single CPU is always coherent
with itself, so on a non-SMP case we don't need those barriers.
However, there are a few places where the barriers in use (GMMU
page table programming, IO accessors, userd) where the barrier
usage is for communicating and establishing ordering for the
GPU. We need these barriers for both SMP machines and non-SMP
machines. Therefor we must use the plain barrier versions.
Change-Id: I376129840b7dc64af8f3f23f88057e4e81360f89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599744
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/io.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/io.c b/drivers/gpu/nvgpu/common/linux/io.c index 04a9fbe8..729825e7 100644 --- a/drivers/gpu/nvgpu/common/linux/io.c +++ b/drivers/gpu/nvgpu/common/linux/io.c | |||
@@ -26,7 +26,7 @@ void nvgpu_writel(struct gk20a *g, u32 r, u32 v) | |||
26 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); | 26 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); |
27 | } else { | 27 | } else { |
28 | writel_relaxed(v, l->regs + r); | 28 | writel_relaxed(v, l->regs + r); |
29 | nvgpu_smp_wmb(); | 29 | nvgpu_wmb(); |
30 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); | 30 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); |
31 | } | 31 | } |
32 | } | 32 | } |
@@ -57,7 +57,7 @@ void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v) | |||
57 | __gk20a_warn_on_no_regs(); | 57 | __gk20a_warn_on_no_regs(); |
58 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); | 58 | gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); |
59 | } else { | 59 | } else { |
60 | nvgpu_smp_wmb(); | 60 | nvgpu_wmb(); |
61 | do { | 61 | do { |
62 | writel_relaxed(v, l->regs + r); | 62 | writel_relaxed(v, l->regs + r); |
63 | } while (readl(l->regs + r) != v); | 63 | } while (readl(l->regs + r) != v); |
@@ -73,7 +73,7 @@ void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v) | |||
73 | __gk20a_warn_on_no_regs(); | 73 | __gk20a_warn_on_no_regs(); |
74 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); | 74 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); |
75 | } else { | 75 | } else { |
76 | nvgpu_smp_wmb(); | 76 | nvgpu_wmb(); |
77 | writel_relaxed(v, l->bar1 + b); | 77 | writel_relaxed(v, l->bar1 + b); |
78 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); | 78 | gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); |
79 | } | 79 | } |