diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2018-03-26 21:23:52 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-24 07:35:53 -0400 |
commit | 9ae69536b997db1ffa5ef81599a73e164efe8b9d (patch) | |
tree | f89e8dfe1f638302581f2d46e8ab215aad0cad3f /drivers/gpu/nvgpu/common/linux | |
parent | 67c4571d959ec1066cbacb7f9ff1c19ea5fdd079 (diff) |
gpu: nvgpu: gv11b: chip revision check for invalidates
Only for T194 A01 version following invalidates are disabled:
-CBM alpha and beta invalidations for L2
-SCC pagepool invalidates
-SWDX spill buffer invalidates
Bug 2053668
Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680500
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/soc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/soc.c b/drivers/gpu/nvgpu/common/linux/soc.c index 305d8bd9..1b27d6f1 100644 --- a/drivers/gpu/nvgpu/common/linux/soc.c +++ b/drivers/gpu/nvgpu/common/linux/soc.c | |||
@@ -12,6 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <soc/tegra/chip-id.h> | 14 | #include <soc/tegra/chip-id.h> |
15 | #include <soc/tegra/fuse.h> | ||
15 | #include <soc/tegra/tegra_bpmp.h> | 16 | #include <soc/tegra/tegra_bpmp.h> |
16 | #ifdef CONFIG_TEGRA_HV_MANAGER | 17 | #ifdef CONFIG_TEGRA_HV_MANAGER |
17 | #include <soc/tegra/virt/syscalls.h> | 18 | #include <soc/tegra/virt/syscalls.h> |
@@ -46,6 +47,13 @@ bool nvgpu_is_bpmp_running(struct gk20a *g) | |||
46 | return tegra_bpmp_running(); | 47 | return tegra_bpmp_running(); |
47 | } | 48 | } |
48 | 49 | ||
50 | bool nvgpu_is_soc_t194_a01(struct gk20a *g) | ||
51 | { | ||
52 | return ((tegra_get_chip_id() == TEGRA194 && | ||
53 | tegra_chip_get_revision() == TEGRA194_REVISION_A01) ? | ||
54 | true : false); | ||
55 | } | ||
56 | |||
49 | #ifdef CONFIG_TEGRA_HV_MANAGER | 57 | #ifdef CONFIG_TEGRA_HV_MANAGER |
50 | /* When nvlink is enabled on dGPU, we need to use physical memory addresses. | 58 | /* When nvlink is enabled on dGPU, we need to use physical memory addresses. |
51 | * There is no SMMU translation. However, the device initially enumerates as a | 59 | * There is no SMMU translation. However, the device initially enumerates as a |