diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-25 06:08:49 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-07 12:45:14 -0400 |
commit | 15ec5722be8f483f6d9c1cd0bfd61a7e2bcbfca2 (patch) | |
tree | 8bc083a63442113d8a9773b555ae3d1bff8958df /drivers/gpu/nvgpu/common/linux | |
parent | bb7ed28ab17ce68c71838bc2aa3fd6e2a0a71a15 (diff) |
gpu: nvgpu: add HAL to handle nonstall interrupts
Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts
We already handle nonstall interrupts in nvgpu_intr_nonstall()
But this API is completely in linux specific code
Separate out os-independent code to handle nonstall interrupts in new API
mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all
existing chips
Call this HAL from nvgpu_intr_nonstall()
Jira NVGPUT-8
Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1706589
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/intr.c | 35 |
1 files changed, 4 insertions, 31 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/intr.c b/drivers/gpu/nvgpu/common/linux/intr.c index 6b4b2dc9..05dd3f2a 100644 --- a/drivers/gpu/nvgpu/common/linux/intr.c +++ b/drivers/gpu/nvgpu/common/linux/intr.c | |||
@@ -69,11 +69,8 @@ irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g) | |||
69 | 69 | ||
70 | irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) | 70 | irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) |
71 | { | 71 | { |
72 | u32 mc_intr_1; | 72 | u32 non_stall_intr_val; |
73 | u32 hw_irq_count; | 73 | u32 hw_irq_count; |
74 | u32 engine_id_idx; | ||
75 | u32 active_engine_id = 0; | ||
76 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
77 | int ops_old, ops_new, ops = 0; | 74 | int ops_old, ops_new, ops = 0; |
78 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 75 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
79 | 76 | ||
@@ -81,37 +78,13 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) | |||
81 | return IRQ_NONE; | 78 | return IRQ_NONE; |
82 | 79 | ||
83 | /* not from gpu when sharing irq with others */ | 80 | /* not from gpu when sharing irq with others */ |
84 | mc_intr_1 = g->ops.mc.intr_nonstall(g); | 81 | non_stall_intr_val = g->ops.mc.intr_nonstall(g); |
85 | if (unlikely(!mc_intr_1)) | 82 | if (unlikely(!non_stall_intr_val)) |
86 | return IRQ_NONE; | 83 | return IRQ_NONE; |
87 | 84 | ||
88 | g->ops.mc.intr_nonstall_pause(g); | 85 | g->ops.mc.intr_nonstall_pause(g); |
89 | 86 | ||
90 | if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) | 87 | ops = g->ops.mc.isr_nonstall(g); |
91 | ops |= gk20a_fifo_nonstall_isr(g); | ||
92 | |||
93 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; | ||
94 | engine_id_idx++) { | ||
95 | struct fifo_engine_info_gk20a *engine_info; | ||
96 | |||
97 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
98 | engine_info = &g->fifo.engine_info[active_engine_id]; | ||
99 | |||
100 | if (mc_intr_1 & engine_info->intr_mask) { | ||
101 | engine_enum = engine_info->engine_enum; | ||
102 | /* GR Engine */ | ||
103 | if (engine_enum == ENGINE_GR_GK20A) | ||
104 | ops |= gk20a_gr_nonstall_isr(g); | ||
105 | |||
106 | /* CE Engine */ | ||
107 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
108 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
109 | g->ops.ce2.isr_nonstall) | ||
110 | ops |= g->ops.ce2.isr_nonstall(g, | ||
111 | engine_info->inst_id, | ||
112 | engine_info->pri_base); | ||
113 | } | ||
114 | } | ||
115 | if (ops) { | 88 | if (ops) { |
116 | do { | 89 | do { |
117 | ops_old = atomic_read(&l->nonstall_ops); | 90 | ops_old = atomic_read(&l->nonstall_ops); |