diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-12-15 12:04:15 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-17 15:29:09 -0500 |
commit | 2f6698b863c9cc1db6455637b7c72e812b470b93 (patch) | |
tree | d0c8abf32d6994b9f54bf5eddafd8316e038c829 /drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h | |
parent | 6a73114788ffafe4c53771c707ecbd9c9ea0a117 (diff) |
gpu: nvgpu: Make graphics context property of TSG
Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.
Bug 1842197
Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h index 8c306ea0..20624240 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h | |||
@@ -79,12 +79,12 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | |||
79 | int vgpu_gr_nonstall_isr(struct gk20a *g, | 79 | int vgpu_gr_nonstall_isr(struct gk20a *g, |
80 | struct tegra_vgpu_gr_nonstall_intr_info *info); | 80 | struct tegra_vgpu_gr_nonstall_intr_info *info); |
81 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | 81 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, |
82 | struct gr_ctx_desc **__gr_ctx, | 82 | struct nvgpu_gr_ctx *gr_ctx, |
83 | struct vm_gk20a *vm, | 83 | struct vm_gk20a *vm, |
84 | u32 class, | 84 | u32 class, |
85 | u32 flags); | 85 | u32 flags); |
86 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | 86 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, |
87 | struct gr_ctx_desc *gr_ctx); | 87 | struct nvgpu_gr_ctx *gr_ctx); |
88 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | 88 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, |
89 | struct tegra_vgpu_sm_esr_info *info); | 89 | struct tegra_vgpu_sm_esr_info *info); |
90 | int vgpu_gr_init_ctx_state(struct gk20a *g); | 90 | int vgpu_gr_init_ctx_state(struct gk20a *g); |
@@ -141,7 +141,7 @@ static inline int vgpu_gr_isr(struct gk20a *g, | |||
141 | return 0; | 141 | return 0; |
142 | } | 142 | } |
143 | static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | 143 | static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, |
144 | struct gr_ctx_desc **__gr_ctx, | 144 | struct nvgpu_gr_ctx *gr_ctx, |
145 | struct vm_gk20a *vm, | 145 | struct vm_gk20a *vm, |
146 | u32 class, | 146 | u32 class, |
147 | u32 flags) | 147 | u32 flags) |
@@ -149,7 +149,7 @@ static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | |||
149 | return -ENOSYS; | 149 | return -ENOSYS; |
150 | } | 150 | } |
151 | static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | 151 | static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, |
152 | struct gr_ctx_desc *gr_ctx) | 152 | struct nvgpu_gr_ctx *gr_ctx) |
153 | { | 153 | { |
154 | } | 154 | } |
155 | static inline int vgpu_gr_init_ctx_state(struct gk20a *g) | 155 | static inline int vgpu_gr_init_ctx_state(struct gk20a *g) |