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authorDeepak Nibade <dnibade@nvidia.com>2017-11-14 09:43:28 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-17 11:27:19 -0500
commitb42fb7ba26b565f93118fbdd9e17b42ee6144c5e (patch)
tree26e2d919f019d15b51bba4d7b5c938f77ad5cff5 /drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
parentb7cc3a2aa6c92a09eed43513287c9062f22ad127 (diff)
gpu: nvgpu: move vgpu code to linux
Most of VGPU code is linux specific but lies in common code So until VGPU code is properly abstracted and made os-independent, move all of VGPU code to linux specific directory Handle corresponding Makefile changes Update all #includes to reflect new paths Add GPL license to newly added linux files Jira NVGPU-387 Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599472 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c637
1 files changed, 637 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
new file mode 100644
index 00000000..6b5a1b0d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -0,0 +1,637 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <gk20a/gk20a.h>
18#include <gv11b/hal_gv11b.h>
19
20#include "common/linux/vgpu/vgpu.h"
21#include "common/linux/vgpu/fifo_vgpu.h"
22#include "common/linux/vgpu/gr_vgpu.h"
23#include "common/linux/vgpu/ltc_vgpu.h"
24#include "common/linux/vgpu/mm_vgpu.h"
25#include "common/linux/vgpu/dbg_vgpu.h"
26#include "common/linux/vgpu/fecs_trace_vgpu.h"
27#include "common/linux/vgpu/css_vgpu.h"
28#include "common/linux/vgpu/vgpu_t19x.h"
29#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
30#include "common/linux/vgpu/gp10b/vgpu_mm_gp10b.h"
31#include "common/linux/vgpu/gp10b/vgpu_gr_gp10b.h"
32
33#include <gk20a/fb_gk20a.h>
34#include <gk20a/flcn_gk20a.h>
35#include <gk20a/bus_gk20a.h>
36#include <gk20a/mc_gk20a.h>
37
38#include <gm20b/gr_gm20b.h>
39#include <gm20b/fb_gm20b.h>
40#include <gm20b/fifo_gm20b.h>
41#include <gm20b/pmu_gm20b.h>
42#include <gm20b/mm_gm20b.h>
43#include <gm20b/acr_gm20b.h>
44#include <gm20b/ltc_gm20b.h>
45
46#include <gp10b/fb_gp10b.h>
47#include <gp10b/pmu_gp10b.h>
48#include <gp10b/mm_gp10b.h>
49#include <gp10b/mc_gp10b.h>
50#include <gp10b/ce_gp10b.h>
51#include <gp10b/fifo_gp10b.h>
52#include <gp10b/therm_gp10b.h>
53#include <gp10b/priv_ring_gp10b.h>
54#include <gp10b/ltc_gp10b.h>
55
56#include <gp106/pmu_gp106.h>
57#include <gp106/acr_gp106.h>
58
59#include <gv11b/fb_gv11b.h>
60#include <gv11b/pmu_gv11b.h>
61#include <gv11b/acr_gv11b.h>
62#include <gv11b/mm_gv11b.h>
63#include <gv11b/mc_gv11b.h>
64#include <gv11b/ce_gv11b.h>
65#include <gv11b/fifo_gv11b.h>
66#include <gv11b/therm_gv11b.h>
67#include <gv11b/regops_gv11b.h>
68#include <gv11b/gr_ctx_gv11b.h>
69#include <gv11b/ltc_gv11b.h>
70#include <gv11b/gv11b_gating_reglist.h>
71
72#include <gv100/gr_gv100.h>
73
74#include <nvgpu/enabled.h>
75
76#include "vgpu_gv11b.h"
77#include "vgpu_gr_gv11b.h"
78#include "vgpu_fifo_gv11b.h"
79#include "vgpu_subctx_gv11b.h"
80#include "vgpu_tsg_gv11b.h"
81
82#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
83#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
84#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
85#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
86#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
87
88static const struct gpu_ops vgpu_gv11b_ops = {
89 .ltc = {
90 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
91 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
92 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
93 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
94 .init_cbc = NULL,
95 .init_fs_state = vgpu_ltc_init_fs_state,
96 .init_comptags = vgpu_ltc_init_comptags,
97 .cbc_ctrl = NULL,
98 .isr = gv11b_ltc_isr,
99 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
100 .flush = gm20b_flush_ltc,
101 .set_enabled = gp10b_ltc_set_enabled,
102 },
103 .ce2 = {
104 .isr_stall = gv11b_ce_isr,
105 .isr_nonstall = gp10b_ce_nonstall_isr,
106 .get_num_pce = vgpu_ce_get_num_pce,
107 },
108 .gr = {
109 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
110 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
111 .cb_size_default = gr_gv11b_cb_size_default,
112 .calc_global_ctx_buffer_size =
113 gr_gv11b_calc_global_ctx_buffer_size,
114 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
115 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
116 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
117 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
118 .handle_sw_method = gr_gv11b_handle_sw_method,
119 .set_alpha_circular_buffer_size =
120 gr_gv11b_set_alpha_circular_buffer_size,
121 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
122 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
123 .is_valid_class = gr_gv11b_is_valid_class,
124 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
125 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
126 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
127 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
128 .init_fs_state = vgpu_gm20b_init_fs_state,
129 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
130 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
131 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
132 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
133 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
134 .free_channel_ctx = vgpu_gr_free_channel_ctx,
135 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
136 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
137 .get_zcull_info = vgpu_gr_get_zcull_info,
138 .is_tpc_addr = gr_gm20b_is_tpc_addr,
139 .get_tpc_num = gr_gm20b_get_tpc_num,
140 .detect_sm_arch = vgpu_gr_detect_sm_arch,
141 .add_zbc_color = gr_gp10b_add_zbc_color,
142 .add_zbc_depth = gr_gp10b_add_zbc_depth,
143 .zbc_set_table = vgpu_gr_add_zbc,
144 .zbc_query_table = vgpu_gr_query_zbc,
145 .pmu_save_zbc = gk20a_pmu_save_zbc,
146 .add_zbc = gr_gk20a_add_zbc,
147 .pagepool_default_size = gr_gv11b_pagepool_default_size,
148 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
149 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
150 .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx,
151 .update_ctxsw_preemption_mode =
152 gr_gp10b_update_ctxsw_preemption_mode,
153 .dump_gr_regs = NULL,
154 .update_pc_sampling = gr_gm20b_update_pc_sampling,
155 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
156 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
157 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
158 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
159 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
160 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
161 .wait_empty = gr_gv11b_wait_empty,
162 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
163 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
164 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
165 .bpt_reg_info = gv11b_gr_bpt_reg_info,
166 .get_access_map = gr_gv11b_get_access_map,
167 .handle_fecs_error = gr_gv11b_handle_fecs_error,
168 .handle_sm_exception = gr_gk20a_handle_sm_exception,
169 .handle_tex_exception = gr_gv11b_handle_tex_exception,
170 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
171 .enable_exceptions = gr_gv11b_enable_exceptions,
172 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
173 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
174 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
175 .record_sm_error_state = gv11b_gr_record_sm_error_state,
176 .update_sm_error_state = gv11b_gr_update_sm_error_state,
177 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
178 .suspend_contexts = vgpu_gr_suspend_contexts,
179 .resume_contexts = vgpu_gr_resume_contexts,
180 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
181 .init_sm_id_table = gr_gv100_init_sm_id_table,
182 .load_smid_config = gr_gv11b_load_smid_config,
183 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
184 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
185 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
186 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
187 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
188 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
189 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
190 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
191 .commit_inst = vgpu_gr_gv11b_commit_inst,
192 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
193 .write_pm_ptr = gr_gv11b_write_pm_ptr,
194 .init_elcg_mode = gr_gv11b_init_elcg_mode,
195 .load_tpc_mask = gr_gv11b_load_tpc_mask,
196 .inval_icache = gr_gk20a_inval_icache,
197 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
198 .wait_for_pause = gr_gk20a_wait_for_pause,
199 .resume_from_pause = gv11b_gr_resume_from_pause,
200 .clear_sm_errors = gr_gk20a_clear_sm_errors,
201 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
202 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
203 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
204 .suspend_single_sm = gv11b_gr_suspend_single_sm,
205 .suspend_all_sms = gv11b_gr_suspend_all_sms,
206 .resume_single_sm = gv11b_gr_resume_single_sm,
207 .resume_all_sms = gv11b_gr_resume_all_sms,
208 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
209 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
210 .get_sm_no_lock_down_hww_global_esr_mask =
211 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
212 .lock_down_sm = gv11b_gr_lock_down_sm,
213 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
214 .clear_sm_hww = gv11b_gr_clear_sm_hww,
215 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
216 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
217 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
218 .set_boosted_ctx = NULL,
219 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
220 .set_czf_bypass = NULL,
221 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
222 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
223 .init_preemption_state = NULL,
224 .update_boosted_ctx = NULL,
225 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
226 .create_gr_sysfs = gr_gv11b_create_sysfs,
227 .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
228 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
229 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
230 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
231 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
232 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
233 .handle_gpc_gpcmmu_exception =
234 gr_gv11b_handle_gpc_gpcmmu_exception,
235 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
236 .get_egpc_base = gv11b_gr_get_egpc_base,
237 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
238 .handle_gpc_gpccs_exception =
239 gr_gv11b_handle_gpc_gpccs_exception,
240 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
241 .access_smpc_reg = gv11b_gr_access_smpc_reg,
242 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
243 .add_zbc_s = gr_gv11b_add_zbc_stencil,
244 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
245 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
246 .handle_tpc_sm_ecc_exception =
247 gr_gv11b_handle_tpc_sm_ecc_exception,
248 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
249 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
250 },
251 .fb = {
252 .reset = gv11b_fb_reset,
253 .init_hw = gk20a_fb_init_hw,
254 .init_fs_state = gv11b_fb_init_fs_state,
255 .init_cbc = gv11b_fb_init_cbc,
256 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
257 .set_use_full_comp_tag_line =
258 gm20b_fb_set_use_full_comp_tag_line,
259 .compression_page_size = gp10b_fb_compression_page_size,
260 .compressible_page_size = gp10b_fb_compressible_page_size,
261 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
262 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
263 .read_wpr_info = gm20b_fb_read_wpr_info,
264 .is_debug_mode_enabled = NULL,
265 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
266 .tlb_invalidate = vgpu_mm_tlb_invalidate,
267 .hub_isr = gv11b_fb_hub_isr,
268 },
269 .clock_gating = {
270 .slcg_bus_load_gating_prod =
271 gv11b_slcg_bus_load_gating_prod,
272 .slcg_ce2_load_gating_prod =
273 gv11b_slcg_ce2_load_gating_prod,
274 .slcg_chiplet_load_gating_prod =
275 gv11b_slcg_chiplet_load_gating_prod,
276 .slcg_ctxsw_firmware_load_gating_prod =
277 gv11b_slcg_ctxsw_firmware_load_gating_prod,
278 .slcg_fb_load_gating_prod =
279 gv11b_slcg_fb_load_gating_prod,
280 .slcg_fifo_load_gating_prod =
281 gv11b_slcg_fifo_load_gating_prod,
282 .slcg_gr_load_gating_prod =
283 gr_gv11b_slcg_gr_load_gating_prod,
284 .slcg_ltc_load_gating_prod =
285 ltc_gv11b_slcg_ltc_load_gating_prod,
286 .slcg_perf_load_gating_prod =
287 gv11b_slcg_perf_load_gating_prod,
288 .slcg_priring_load_gating_prod =
289 gv11b_slcg_priring_load_gating_prod,
290 .slcg_pmu_load_gating_prod =
291 gv11b_slcg_pmu_load_gating_prod,
292 .slcg_therm_load_gating_prod =
293 gv11b_slcg_therm_load_gating_prod,
294 .slcg_xbar_load_gating_prod =
295 gv11b_slcg_xbar_load_gating_prod,
296 .blcg_bus_load_gating_prod =
297 gv11b_blcg_bus_load_gating_prod,
298 .blcg_ce_load_gating_prod =
299 gv11b_blcg_ce_load_gating_prod,
300 .blcg_ctxsw_firmware_load_gating_prod =
301 gv11b_blcg_ctxsw_firmware_load_gating_prod,
302 .blcg_fb_load_gating_prod =
303 gv11b_blcg_fb_load_gating_prod,
304 .blcg_fifo_load_gating_prod =
305 gv11b_blcg_fifo_load_gating_prod,
306 .blcg_gr_load_gating_prod =
307 gv11b_blcg_gr_load_gating_prod,
308 .blcg_ltc_load_gating_prod =
309 gv11b_blcg_ltc_load_gating_prod,
310 .blcg_pwr_csb_load_gating_prod =
311 gv11b_blcg_pwr_csb_load_gating_prod,
312 .blcg_pmu_load_gating_prod =
313 gv11b_blcg_pmu_load_gating_prod,
314 .blcg_xbar_load_gating_prod =
315 gv11b_blcg_xbar_load_gating_prod,
316 .pg_gr_load_gating_prod =
317 gr_gv11b_pg_gr_load_gating_prod,
318 },
319 .fifo = {
320 .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
321 .bind_channel = vgpu_channel_bind,
322 .unbind_channel = vgpu_channel_unbind,
323 .disable_channel = vgpu_channel_disable,
324 .enable_channel = vgpu_channel_enable,
325 .alloc_inst = vgpu_channel_alloc_inst,
326 .free_inst = vgpu_channel_free_inst,
327 .setup_ramfc = vgpu_channel_setup_ramfc,
328 .channel_set_timeslice = vgpu_channel_set_timeslice,
329 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
330 .setup_userd = gk20a_fifo_setup_userd,
331 .userd_gp_get = gv11b_userd_gp_get,
332 .userd_gp_put = gv11b_userd_gp_put,
333 .userd_pb_get = gv11b_userd_pb_get,
334 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
335 .preempt_channel = vgpu_fifo_preempt_channel,
336 .preempt_tsg = vgpu_fifo_preempt_tsg,
337 .enable_tsg = vgpu_enable_tsg,
338 .disable_tsg = gk20a_disable_tsg,
339 .tsg_verify_channel_status = NULL,
340 .tsg_verify_status_ctx_reload = NULL,
341 /* TODO: implement it for CE fault */
342 .tsg_verify_status_faulted = NULL,
343 .update_runlist = vgpu_fifo_update_runlist,
344 .trigger_mmu_fault = NULL,
345 .get_mmu_fault_info = NULL,
346 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
347 .get_num_fifos = gv11b_fifo_get_num_fifos,
348 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
349 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
350 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
351 .tsg_open = vgpu_tsg_open,
352 .force_reset_ch = vgpu_fifo_force_reset_ch,
353 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
354 .device_info_data_parse = gp10b_device_info_data_parse,
355 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
356 .init_engine_info = vgpu_fifo_init_engine_info,
357 .runlist_entry_size = ram_rl_entry_size_v,
358 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
359 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
360 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
361 .dump_pbdma_status = gk20a_dump_pbdma_status,
362 .dump_eng_status = gv11b_dump_eng_status,
363 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
364 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
365 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
366 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
367 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
368 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
369 .handle_sched_error = gv11b_fifo_handle_sched_error,
370 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
371 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
372 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
373 .deinit_eng_method_buffers =
374 gv11b_fifo_deinit_eng_method_buffers,
375 .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
376 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
377#ifdef CONFIG_TEGRA_GK20A_NVHOST
378 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
379 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
380 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
381 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
382 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
383 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
384#endif
385 .resetup_ramfc = NULL,
386 .reschedule_runlist = NULL,
387 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
388 .free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
389 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
390 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
391 },
392 .gr_ctx = {
393 .get_netlist_name = gr_gv11b_get_netlist_name,
394 .is_fw_defined = gr_gv11b_is_firmware_defined,
395 },
396#ifdef CONFIG_GK20A_CTXSW_TRACE
397 .fecs_trace = {
398 .alloc_user_buffer = NULL,
399 .free_user_buffer = NULL,
400 .mmap_user_buffer = NULL,
401 .init = NULL,
402 .deinit = NULL,
403 .enable = NULL,
404 .disable = NULL,
405 .is_enabled = NULL,
406 .reset = NULL,
407 .flush = NULL,
408 .poll = NULL,
409 .bind_channel = NULL,
410 .unbind_channel = NULL,
411 .max_entries = NULL,
412 },
413#endif /* CONFIG_GK20A_CTXSW_TRACE */
414 .mm = {
415 /* FIXME: add support for sparse mappings */
416 .support_sparse = NULL,
417 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
418 .gmmu_unmap = vgpu_locked_gmmu_unmap,
419 .vm_bind_channel = vgpu_vm_bind_channel,
420 .fb_flush = vgpu_mm_fb_flush,
421 .l2_invalidate = vgpu_mm_l2_invalidate,
422 .l2_flush = vgpu_mm_l2_flush,
423 .cbc_clean = gk20a_mm_cbc_clean,
424 .set_big_page_size = gm20b_mm_set_big_page_size,
425 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
426 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
427 .gpu_phys_addr = gm20b_gpu_phys_addr,
428 .get_iommu_bit = gk20a_mm_get_iommu_bit,
429 .get_mmu_levels = gp10b_mm_get_mmu_levels,
430 .init_pdb = gp10b_mm_init_pdb,
431 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
432 .is_bar1_supported = gv11b_mm_is_bar1_supported,
433 .init_inst_block = gv11b_init_inst_block,
434 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
435 .get_kind_invalid = gm20b_get_kind_invalid,
436 .get_kind_pitch = gm20b_get_kind_pitch,
437 .init_bar2_vm = gb10b_init_bar2_vm,
438 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
439 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
440 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
441 },
442 .therm = {
443 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
444 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
445 },
446 .pmu = {
447 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
448 .pmu_get_queue_head = pwr_pmu_queue_head_r,
449 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
450 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
451 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
452 .pmu_queue_head = gk20a_pmu_queue_head,
453 .pmu_queue_tail = gk20a_pmu_queue_tail,
454 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
455 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
456 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
457 .pmu_mutex_release = gk20a_pmu_mutex_release,
458 .write_dmatrfbase = gp10b_write_dmatrfbase,
459 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
460 .pmu_pg_init_param = gv11b_pg_gr_init,
461 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
462 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
463 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
464 .reset_engine = gp106_pmu_engine_reset,
465 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
466 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
467 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
468 .is_pmu_supported = gv11b_is_pmu_supported,
469 },
470 .regops = {
471 .get_global_whitelist_ranges =
472 gv11b_get_global_whitelist_ranges,
473 .get_global_whitelist_ranges_count =
474 gv11b_get_global_whitelist_ranges_count,
475 .get_context_whitelist_ranges =
476 gv11b_get_context_whitelist_ranges,
477 .get_context_whitelist_ranges_count =
478 gv11b_get_context_whitelist_ranges_count,
479 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
480 .get_runcontrol_whitelist_count =
481 gv11b_get_runcontrol_whitelist_count,
482 .get_runcontrol_whitelist_ranges =
483 gv11b_get_runcontrol_whitelist_ranges,
484 .get_runcontrol_whitelist_ranges_count =
485 gv11b_get_runcontrol_whitelist_ranges_count,
486 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
487 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
488 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
489 .get_qctl_whitelist_ranges_count =
490 gv11b_get_qctl_whitelist_ranges_count,
491 .apply_smpc_war = gv11b_apply_smpc_war,
492 },
493 .mc = {
494 .intr_enable = mc_gv11b_intr_enable,
495 .intr_unit_config = mc_gp10b_intr_unit_config,
496 .isr_stall = mc_gp10b_isr_stall,
497 .intr_stall = mc_gp10b_intr_stall,
498 .intr_stall_pause = mc_gp10b_intr_stall_pause,
499 .intr_stall_resume = mc_gp10b_intr_stall_resume,
500 .intr_nonstall = mc_gp10b_intr_nonstall,
501 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
502 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
503 .enable = gk20a_mc_enable,
504 .disable = gk20a_mc_disable,
505 .reset = gk20a_mc_reset,
506 .boot_0 = gk20a_mc_boot_0,
507 .is_intr1_pending = mc_gp10b_is_intr1_pending,
508 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
509 },
510 .debug = {
511 .show_dump = NULL,
512 },
513 .dbg_session_ops = {
514 .exec_reg_ops = vgpu_exec_regops,
515 .dbg_set_powergate = vgpu_dbg_set_powergate,
516 .check_and_set_global_reservation =
517 vgpu_check_and_set_global_reservation,
518 .check_and_set_context_reservation =
519 vgpu_check_and_set_context_reservation,
520 .release_profiler_reservation =
521 vgpu_release_profiler_reservation,
522 .perfbuffer_enable = vgpu_perfbuffer_enable,
523 .perfbuffer_disable = vgpu_perfbuffer_disable,
524 },
525 .bus = {
526 .init_hw = gk20a_bus_init_hw,
527 .isr = gk20a_bus_isr,
528 .read_ptimer = vgpu_read_ptimer,
529 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
530 .bar1_bind = NULL,
531 },
532#if defined(CONFIG_GK20A_CYCLE_STATS)
533 .css = {
534 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
535 .disable_snapshot = vgpu_css_release_snapshot_buffer,
536 .check_data_available = vgpu_css_flush_snapshots,
537 .set_handled_snapshots = NULL,
538 .allocate_perfmon_ids = NULL,
539 .release_perfmon_ids = NULL,
540 },
541#endif
542 .falcon = {
543 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
544 },
545 .priv_ring = {
546 .isr = gp10b_priv_ring_isr,
547 },
548 .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
549 .get_litter_value = gv11b_get_litter_value,
550};
551
552int vgpu_gv11b_init_hal(struct gk20a *g)
553{
554 struct gpu_ops *gops = &g->ops;
555 u32 val;
556 bool priv_security;
557
558 gops->ltc = vgpu_gv11b_ops.ltc;
559 gops->ce2 = vgpu_gv11b_ops.ce2;
560 gops->gr = vgpu_gv11b_ops.gr;
561 gops->fb = vgpu_gv11b_ops.fb;
562 gops->clock_gating = vgpu_gv11b_ops.clock_gating;
563 gops->fifo = vgpu_gv11b_ops.fifo;
564 gops->gr_ctx = vgpu_gv11b_ops.gr_ctx;
565 gops->mm = vgpu_gv11b_ops.mm;
566 gops->fecs_trace = vgpu_gv11b_ops.fecs_trace;
567 gops->therm = vgpu_gv11b_ops.therm;
568 gops->pmu = vgpu_gv11b_ops.pmu;
569 gops->regops = vgpu_gv11b_ops.regops;
570 gops->mc = vgpu_gv11b_ops.mc;
571 gops->debug = vgpu_gv11b_ops.debug;
572 gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
573 gops->bus = vgpu_gv11b_ops.bus;
574#if defined(CONFIG_GK20A_CYCLE_STATS)
575 gops->css = vgpu_gv11b_ops.css;
576#endif
577 gops->falcon = vgpu_gv11b_ops.falcon;
578 gops->priv_ring = vgpu_gv11b_ops.priv_ring;
579
580 /* Lone functions */
581 gops->chip_init_gpu_characteristics =
582 vgpu_gv11b_ops.chip_init_gpu_characteristics;
583 gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
584
585 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
586 if (val) {
587 priv_security = true;
588 pr_err("priv security is enabled\n");
589 } else {
590 priv_security = false;
591 pr_err("priv security is disabled\n");
592 }
593 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
594 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security);
595 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security);
596
597 /* priv security dependent ops */
598 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
599 /* Add in ops from gm20b acr */
600 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
601 gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
602 gops->pmu.get_wpr = gm20b_wpr_info,
603 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
604 gops->pmu.pmu_populate_loader_cfg =
605 gp106_pmu_populate_loader_cfg,
606 gops->pmu.flcn_populate_bl_dmem_desc =
607 gp106_flcn_populate_bl_dmem_desc,
608 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
609 gops->pmu.falcon_clear_halt_interrupt_status =
610 clear_halt_interrupt_status,
611 gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
612
613 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
614 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
615 gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap,
616 gops->pmu.is_priv_load = gv11b_is_priv_load,
617
618 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
619 } else {
620 /* Inherit from gk20a */
621 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
622 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
623
624 gops->pmu.load_lsfalcon_ucode = NULL;
625 gops->pmu.init_wpr_region = NULL;
626 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
627
628 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
629 }
630
631 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
632 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
633
634 g->name = "gv11b";
635
636 return 0;
637}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 18:32:00 -0400