diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-12-30 16:04:19 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-10 18:57:20 -0500 |
commit | 6b90684ceec6c32aed7491a059b3972b1f1be5f4 (patch) | |
tree | 0bc0fa73de0e352d8da8f360cac780c903c60d95 /drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |
parent | 5fb7c7d8f97bbec0d01f4f26aaf7757790c8b407 (diff) |
gpu: nvgpu: vgpu: get virtual SMs mapping
On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in
vgpu constants to properly dimension the virtual SM to TPC/GPC
mapping in virtualization case.
Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping.
Bug 2039676
Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631203
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index 1523c2de..6f85b4ee 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -126,7 +126,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
126 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | 126 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, |
127 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | 127 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, |
128 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | 128 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, |
129 | .init_fs_state = vgpu_gm20b_init_fs_state, | 129 | .init_fs_state = vgpu_gr_init_fs_state, |
130 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | 130 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, |
131 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 131 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
132 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 132 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, |
@@ -179,7 +179,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
179 | .suspend_contexts = vgpu_gr_suspend_contexts, | 179 | .suspend_contexts = vgpu_gr_suspend_contexts, |
180 | .resume_contexts = vgpu_gr_resume_contexts, | 180 | .resume_contexts = vgpu_gr_resume_contexts, |
181 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | 181 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, |
182 | .init_sm_id_table = gr_gv100_init_sm_id_table, | 182 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
183 | .load_smid_config = gr_gv11b_load_smid_config, | 183 | .load_smid_config = gr_gv11b_load_smid_config, |
184 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | 184 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, |
185 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | 185 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, |