gpu: nvgpu: Combine gk20a and gp10b free_gr_ctx

gp10b version of free_gr_ctx was created to keep gp10b source code
changes out from the mainline. gp10b was merged back to mainline a
while ago, so this separation is no longer needed. Merge the two
variants.

Change-Id: I954b3b677e98e4248f95641ea22e0def4e583c66
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635127
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 22 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
index a0662956..e8790587 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
@@ -21,6 +21,7 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/dma.h>
 
 #include "vgpu.h"
 #include "gr_vgpu.h"
@@ -317,23 +318,31 @@ int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
 void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
                         struct gr_ctx_desc *gr_ctx)
 {
+        struct tegra_vgpu_cmd_msg msg;
+        struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx;
+        int err;
+
         gk20a_dbg_fn("");
 
-        if (gr_ctx && gr_ctx->mem.gpu_va) {
-                struct tegra_vgpu_cmd_msg msg;
-                struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx;
-                int err;
+        if (!gr_ctx || !gr_ctx->mem.gpu_va)
+                return;
 
-                msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE;
-                msg.handle = vgpu_get_handle(g);
-                p->gr_ctx_handle = gr_ctx->virt_ctx;
-                err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
-                WARN_ON(err || msg.ret);
 
-                __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va,
-                                   gmmu_page_size_kernel);
-                nvgpu_kfree(g, gr_ctx);
-        }
+        msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE;
+        msg.handle = vgpu_get_handle(g);
+        p->gr_ctx_handle = gr_ctx->virt_ctx;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        WARN_ON(err || msg.ret);
+
+        __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va,
+                           gmmu_page_size_kernel);
+
+        nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer);
+        nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer);
+
+        nvgpu_kfree(g, gr_ctx);
 }
 
 static void vgpu_gr_free_channel_gr_ctx(struct channel_gk20a *c)