gpu: nvgpu: Add check_priv_security fuse ops

-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
 and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
 during hal initialization

-For igpu non simulation platforms, fuses are read
 to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
  is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
  in LS mode and this needs wpr_enabled set to 1
  AND vpr_auto_fetch_disable set to 0. In this case
  gmmu tries to pull wpr and vpr settings from tegra mc

Bug 2018223

Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 77 insertions, 18 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c
new file mode 100644
index 00000000..5ee5d1f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/enabled.h>
+
+#include "gk20a/gk20a.h"
+
+int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g)
+{
+        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
+                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
+        } else {
+                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
+                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
+        }
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h
new file mode 100644
index 00000000..2ec8f284
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _VGPU_GP10B_FUSE
+#define _VGPU_GP10B_FUSE
+
+struct gk20a;
+
+int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
index 78f88d4d..b35cac90 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -27,6 +27,7 @@
 #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
 #include "vgpu_gr_gp10b.h"
 #include "vgpu_mm_gp10b.h"
+#include "vgpu_fuse_gp10b.h"
 
 #include "gk20a/bus_gk20a.h"
 #include "gk20a/pramin_gk20a.h"
@@ -498,6 +499,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
         },
+        .fuse = {
+                .check_priv_security = vgpu_gp10b_fuse_check_priv_security,
+        },
         .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
         .get_litter_value = gp10b_get_litter_value,
 };
@@ -505,7 +509,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 int vgpu_gp10b_init_hal(struct gk20a *g)
 {
         struct gpu_ops *gops = &g->ops;
-        u32 val;
 
         gops->ltc = vgpu_gp10b_ops.ltc;
         gops->ce2 = vgpu_gp10b_ops.ce2;
@@ -531,6 +534,8 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 
         gops->priv_ring = vgpu_gp10b_ops.priv_ring;
 
+        gops->fuse = vgpu_gp10b_ops.fuse;
+
         /* Lone Functions */
         gops->chip_init_gpu_characteristics =
                 vgpu_gp10b_ops.chip_init_gpu_characteristics;
@@ -539,23 +544,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
-        } else if (g->is_virtual) {
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-        } else {
-                val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
-                if (val) {
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
-                } else {
-                        gk20a_dbg_info("priv security is disabled in HW");
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
-                }
-        }
+        /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
+        if (gops->fuse.check_priv_security(g))
+                return -EINVAL; /* Do not boot gpu */
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {