summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
diff options
context:
space:
mode:
authorSeema Khowala <seemaj@nvidia.com>2017-11-09 18:32:11 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-22 03:59:18 -0500
commitf34a4d0b125ebf45373e40478925b3eb75b7898a (patch)
treea6bac09ad2f4c38289048acefd724ff2bd3c279f /drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
parentf53a0dd96b25cfb64b17ab816ae1f9b0b144db07 (diff)
gpu: nvgpu: CONFIG_TEGRA_ACR is supported by default
TEGRA_ACR config is supposed to be enabled maxwell onwards. Since gk20a support is no longer supported, delete code that is not under TEGRA_ACR config Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595437 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
index 6806b318..78f88d4d 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -539,7 +539,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
539 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); 539 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
540 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); 540 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
541 541
542#ifdef CONFIG_TEGRA_ACR
543 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 542 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
544 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); 543 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
545 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 544 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
@@ -557,24 +556,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
557 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 556 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
558 } 557 }
559 } 558 }
560#else
561 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
562 gk20a_dbg_info("running simulator with PRIV security disabled");
563 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
564 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
565 } else {
566 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
567 if (val) {
568 gk20a_dbg_info("priv security is not supported but enabled");
569 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
570 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
571 return -EPERM;
572 } else {
573 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
574 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
575 }
576 }
577#endif
578 559
579 /* priv security dependent ops */ 560 /* priv security dependent ops */
580 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { 561 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {