diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-12-30 16:04:19 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-10 18:57:20 -0500 |
commit | 6b90684ceec6c32aed7491a059b3972b1f1be5f4 (patch) | |
tree | 0bc0fa73de0e352d8da8f360cac780c903c60d95 /drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |
parent | 5fb7c7d8f97bbec0d01f4f26aaf7757790c8b407 (diff) |
gpu: nvgpu: vgpu: get virtual SMs mapping
On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in
vgpu constants to properly dimension the virtual SM to TPC/GPC
mapping in virtualization case.
Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping.
Bug 2039676
Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631203
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 66ef6e00..aa520690 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -106,7 +106,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
106 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, | 106 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, |
107 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | 107 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, |
108 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | 108 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, |
109 | .init_fs_state = vgpu_gm20b_init_fs_state, | 109 | .init_fs_state = vgpu_gr_init_fs_state, |
110 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | 110 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, |
111 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 111 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
112 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 112 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, |
@@ -159,7 +159,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
159 | .suspend_contexts = vgpu_gr_suspend_contexts, | 159 | .suspend_contexts = vgpu_gr_suspend_contexts, |
160 | .resume_contexts = vgpu_gr_resume_contexts, | 160 | .resume_contexts = vgpu_gr_resume_contexts, |
161 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | 161 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, |
162 | .init_sm_id_table = gr_gk20a_init_sm_id_table, | 162 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
163 | .load_smid_config = gr_gp10b_load_smid_config, | 163 | .load_smid_config = gr_gp10b_load_smid_config, |
164 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | 164 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, |
165 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | 165 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, |