diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-11-09 17:13:25 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-22 03:59:28 -0500 |
commit | 8fe633449f92d35b60a60de647a4e8fc1b5c8936 (patch) | |
tree | f29ee0ed1c9eba66b99033a17d3b2854662b0a15 /drivers/gpu/nvgpu/common/linux/vgpu/gm20b | |
parent | f34a4d0b125ebf45373e40478925b3eb75b7898a (diff) |
gpu: nvgpu: Add check_priv_security fuse ops
-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
during hal initialization
-For igpu non simulation platforms, fuses are read
to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
in LS mode and this needs wpr_enabled set to 1
AND vpr_auto_fetch_disable set to 0. In this case
gmmu tries to pull wpr and vpr settings from tegra mc
Bug 2018223
Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gm20b')
3 files changed, 76 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c new file mode 100644 index 00000000..2ab745ab --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/enabled.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | |||
27 | int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g) | ||
28 | { | ||
29 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
30 | |||
31 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
32 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
33 | else | ||
34 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
35 | |||
36 | return 0; | ||
37 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h new file mode 100644 index 00000000..39da09fa --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _VGPU_GM20B_FUSE | ||
24 | #define _VGPU_GM20B_FUSE | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g); | ||
29 | |||
30 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index b9d3f734..0e560981 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "common/linux/vgpu/fecs_trace_vgpu.h" | 24 | #include "common/linux/vgpu/fecs_trace_vgpu.h" |
25 | #include "common/linux/vgpu/css_vgpu.h" | 25 | #include "common/linux/vgpu/css_vgpu.h" |
26 | #include "vgpu_gr_gm20b.h" | 26 | #include "vgpu_gr_gm20b.h" |
27 | #include "vgpu_fuse_gm20b.h" | ||
27 | 28 | ||
28 | #include "gk20a/bus_gk20a.h" | 29 | #include "gk20a/bus_gk20a.h" |
29 | #include "gk20a/flcn_gk20a.h" | 30 | #include "gk20a/flcn_gk20a.h" |
@@ -456,6 +457,9 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
456 | .priv_ring = { | 457 | .priv_ring = { |
457 | .isr = gk20a_priv_ring_isr, | 458 | .isr = gk20a_priv_ring_isr, |
458 | }, | 459 | }, |
460 | .fuse = { | ||
461 | .check_priv_security = vgpu_gm20b_fuse_check_priv_security, | ||
462 | }, | ||
459 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | 463 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, |
460 | .get_litter_value = gm20b_get_litter_value, | 464 | .get_litter_value = gm20b_get_litter_value, |
461 | }; | 465 | }; |
@@ -463,7 +467,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
463 | int vgpu_gm20b_init_hal(struct gk20a *g) | 467 | int vgpu_gm20b_init_hal(struct gk20a *g) |
464 | { | 468 | { |
465 | struct gpu_ops *gops = &g->ops; | 469 | struct gpu_ops *gops = &g->ops; |
466 | u32 val; | ||
467 | 470 | ||
468 | gops->ltc = vgpu_gm20b_ops.ltc; | 471 | gops->ltc = vgpu_gm20b_ops.ltc; |
469 | gops->ce2 = vgpu_gm20b_ops.ce2; | 472 | gops->ce2 = vgpu_gm20b_ops.ce2; |
@@ -499,26 +502,19 @@ int vgpu_gm20b_init_hal(struct gk20a *g) | |||
499 | 502 | ||
500 | gops->priv_ring = vgpu_gm20b_ops.priv_ring; | 503 | gops->priv_ring = vgpu_gm20b_ops.priv_ring; |
501 | 504 | ||
505 | gops->fuse = vgpu_gm20b_ops.fuse; | ||
506 | |||
502 | /* Lone functions */ | 507 | /* Lone functions */ |
503 | gops->chip_init_gpu_characteristics = | 508 | gops->chip_init_gpu_characteristics = |
504 | vgpu_gm20b_ops.chip_init_gpu_characteristics; | 509 | vgpu_gm20b_ops.chip_init_gpu_characteristics; |
505 | gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; | 510 | gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; |
506 | 511 | ||
507 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 512 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
508 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
509 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 513 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
510 | 514 | ||
511 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 515 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
512 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 516 | if (gops->fuse.check_priv_security(g)) |
513 | } else { | 517 | return -EINVAL; /* Do not boot gpu */ |
514 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
515 | if (!val) { | ||
516 | gk20a_dbg_info("priv security is disabled in HW"); | ||
517 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
518 | } else { | ||
519 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
520 | } | ||
521 | } | ||
522 | 518 | ||
523 | /* priv security dependent ops */ | 519 | /* priv security dependent ops */ |
524 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 520 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |