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authorSeema Khowala <seemaj@nvidia.com>2017-11-09 18:32:11 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-22 03:59:18 -0500
commitf34a4d0b125ebf45373e40478925b3eb75b7898a (patch)
treea6bac09ad2f4c38289048acefd724ff2bd3c279f /drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
parentf53a0dd96b25cfb64b17ab816ae1f9b0b144db07 (diff)
gpu: nvgpu: CONFIG_TEGRA_ACR is supported by default
TEGRA_ACR config is supposed to be enabled maxwell onwards. Since gk20a support is no longer supported, delete code that is not under TEGRA_ACR config Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595437 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c16
1 files changed, 0 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
index 1a2d378a..b9d3f734 100644
--- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -508,7 +508,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
508 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 508 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
509 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); 509 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
510 510
511#ifdef CONFIG_TEGRA_ACR
512 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 511 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
513 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); 512 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
514 } else { 513 } else {
@@ -520,21 +519,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g)
520 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); 519 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
521 } 520 }
522 } 521 }
523#else
524 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
525 gk20a_dbg_info("running ASIM with PRIV security disabled");
526 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
527 } else {
528 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
529 if (!val) {
530 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
531 } else {
532 gk20a_dbg_info("priv security is not supported but enabled");
533 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
534 return -EPERM;
535 }
536 }
537#endif
538 522
539 /* priv security dependent ops */ 523 /* priv security dependent ops */
540 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { 524 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {