gpu: nvgpu: gv11b: chip revision check for invalidates

Only for T194 A01 version following invalidates are disabled:
-CBM alpha and beta invalidations for L2
-SCC pagepool invalidates
-SWDX spill buffer invalidates

Bug 2053668

Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680500
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/soc.c b/drivers/gpu/nvgpu/common/linux/soc.c
index 305d8bd9..1b27d6f1 100644
--- a/drivers/gpu/nvgpu/common/linux/soc.c
+++ b/drivers/gpu/nvgpu/common/linux/soc.c
@@ -12,6 +12,7 @@
  */
 
 #include <soc/tegra/chip-id.h>
+#include <soc/tegra/fuse.h>
 #include <soc/tegra/tegra_bpmp.h>
 #ifdef CONFIG_TEGRA_HV_MANAGER
 #include <soc/tegra/virt/syscalls.h>
@@ -46,6 +47,13 @@ bool nvgpu_is_bpmp_running(struct gk20a *g)
         return tegra_bpmp_running();
 }
 
+bool nvgpu_is_soc_t194_a01(struct gk20a *g)
+{
+        return ((tegra_get_chip_id() == TEGRA194 &&
+                        tegra_chip_get_revision() == TEGRA194_REVISION_A01) ?
+                true : false);
+}
+
 #ifdef CONFIG_TEGRA_HV_MANAGER
 /* When nvlink is enabled on dGPU, we need to use physical memory addresses.
  * There is no SMMU translation. However, the device initially enumerates as a