gpu: nvgpu: Split non-stall interrupt handling

Split handling of stalling interrupt to Linux specific chip
agnostic and OS independent chip specific parts.

Linux specific chip independent part contains handler for ISR
and passing the control to a bottom half worker. It uses the new MC
HALs intr_nonstall (query interrupt status), intr_nonstall_pause
(pause interrupts), intr_nonstall_resume (resume interrupts), and
is_intr1_pending (query per-engine interrupt bit).

MC HAL isr_nonstall is removed, because its work is now handled in
chip independent code.

JIRA NVGPU-26

Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497048
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index b66a6658..4351ba5b 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -235,7 +235,7 @@ static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
         irqreturn_t ret_nonstall;
 
         ret_stall = nvgpu_intr_stall(g);
-        ret_nonstall = g->ops.mc.isr_nonstall(g);
+        ret_nonstall = nvgpu_intr_nonstall(g);
 
 #if defined(CONFIG_PCI_MSI)
         /* Send MSI EOI */