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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-05-24 18:25:41 -0400
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:07 -0400
commit5215d65c25b5e76c19d9d12b03c52f69e2d40227 (patch)
tree36991e3113ace2bb3c6cd1dc1164c5288412c13d /drivers/gpu/nvgpu/common/linux/pci.c
parentf9a2f449a5f4dd62fcfb1701d69dc40f97a827ff (diff)
gpu: nvgpu: Remove setting of PRI timeout
PRI timeout should always use the HW initialization value. Do not set it explicitly. JIRA NVGPU-588 Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730892 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/pci.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/pci.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index 70125cbc..3d3c2a9f 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -90,7 +90,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
90 .can_slcg = true, 90 .can_slcg = true,
91 .can_blcg = true, 91 .can_blcg = true,
92 .can_elcg = true, 92 .can_elcg = true,
93 .default_pri_timeout = 0x3ff,
94 93
95 .disable_aspm = true, 94 .disable_aspm = true,
96 95
@@ -127,7 +126,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
127 .can_slcg = true, 126 .can_slcg = true,
128 .can_blcg = true, 127 .can_blcg = true,
129 .can_elcg = true, 128 .can_elcg = true,
130 .default_pri_timeout = 0x3ff,
131 129
132 .disable_aspm = true, 130 .disable_aspm = true,
133 131
@@ -164,7 +162,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
164 .can_slcg = true, 162 .can_slcg = true,
165 .can_blcg = true, 163 .can_blcg = true,
166 .can_elcg = true, 164 .can_elcg = true,
167 .default_pri_timeout = 0x3ff,
168 165
169 .disable_aspm = true, 166 .disable_aspm = true,
170 167
@@ -201,7 +198,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
201 .can_slcg = true, 198 .can_slcg = true,
202 .can_blcg = true, 199 .can_blcg = true,
203 .can_elcg = true, 200 .can_elcg = true,
204 .default_pri_timeout = 0x3ff,
205 201
206 .disable_aspm = true, 202 .disable_aspm = true,
207 203
@@ -238,7 +234,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
238 .can_slcg = false, 234 .can_slcg = false,
239 .can_blcg = false, 235 .can_blcg = false,
240 .can_elcg = false, 236 .can_elcg = false,
241 .default_pri_timeout = 0x3ff,
242 237
243 .disable_aspm = true, 238 .disable_aspm = true,
244 239
@@ -273,7 +268,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
273 .can_slcg = false, 268 .can_slcg = false,
274 .can_blcg = false, 269 .can_blcg = false,
275 .can_elcg = false, 270 .can_elcg = false,
276 .default_pri_timeout = 0x3ff,
277 271
278 .disable_aspm = true, 272 .disable_aspm = true,
279 273
@@ -308,7 +302,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
308 .can_slcg = false, 302 .can_slcg = false,
309 .can_blcg = false, 303 .can_blcg = false,
310 .can_elcg = false, 304 .can_elcg = false,
311 .default_pri_timeout = 0x3ff,
312 305
313 .disable_aspm = true, 306 .disable_aspm = true,
314 307
@@ -344,7 +337,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
344 .can_slcg = true, 337 .can_slcg = true,
345 .can_blcg = true, 338 .can_blcg = true,
346 .can_elcg = true, 339 .can_elcg = true,
347 .default_pri_timeout = 0x3ff,
348 340
349 .disable_aspm = true, 341 .disable_aspm = true,
350 342
@@ -380,7 +372,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
380 .can_slcg = false, 372 .can_slcg = false,
381 .can_blcg = false, 373 .can_blcg = false,
382 .can_elcg = false, 374 .can_elcg = false,
383 .default_pri_timeout = 0x3ff,
384 375
385 .disable_aspm = true, 376 .disable_aspm = true,
386 377