diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 15:59:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-06-15 20:47:31 -0400 |
commit | 2a2c16af5f9f1ccfc93a13e820d5381e5c881e92 (patch) | |
tree | 2e5d7b042270a649978e5bb540857012c85fb5b5 /drivers/gpu/nvgpu/common/linux/nvlink.c | |
parent | 98d996f4ffb0137d119b5849cae46d7b7e5693e1 (diff) |
gpu: nvgpu: Move Linux files away from common
Move all Linux source code files to drivers/gpu/nvgpu/os/linux from
drivers/gpu/nvgpu/common/linux. This changes the meaning of common
to be OS independent.
JIRA NVGPU-598
JIRA NVGPU-601
Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747714
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/nvlink.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/nvlink.c | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/nvlink.c b/drivers/gpu/nvgpu/common/linux/nvlink.c deleted file mode 100644 index c93514c0..00000000 --- a/drivers/gpu/nvgpu/common/linux/nvlink.c +++ /dev/null | |||
@@ -1,106 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <gk20a/gk20a.h> | ||
18 | #include <nvgpu/nvlink.h> | ||
19 | #include <nvgpu/enabled.h> | ||
20 | #include "module.h" | ||
21 | |||
22 | #ifdef CONFIG_TEGRA_NVLINK | ||
23 | int nvgpu_nvlink_read_dt_props(struct gk20a *g) | ||
24 | { | ||
25 | struct device_node *np; | ||
26 | struct nvlink_device *ndev = g->nvlink.priv; | ||
27 | u32 local_dev_id; | ||
28 | u32 local_link_id; | ||
29 | u32 remote_dev_id; | ||
30 | u32 remote_link_id; | ||
31 | bool is_master; | ||
32 | |||
33 | /* Parse DT */ | ||
34 | np = nvgpu_get_node(g); | ||
35 | if (!np) | ||
36 | goto fail; | ||
37 | |||
38 | np = of_get_child_by_name(np, "nvidia,nvlink"); | ||
39 | if (!np) | ||
40 | goto fail; | ||
41 | |||
42 | np = of_get_child_by_name(np, "endpoint"); | ||
43 | if (!np) | ||
44 | goto fail; | ||
45 | |||
46 | /* Parse DT structure to detect endpoint topology */ | ||
47 | of_property_read_u32(np, "local_dev_id", &local_dev_id); | ||
48 | of_property_read_u32(np, "local_link_id", &local_link_id); | ||
49 | of_property_read_u32(np, "remote_dev_id", &remote_dev_id); | ||
50 | of_property_read_u32(np, "remote_link_id", &remote_link_id); | ||
51 | is_master = of_property_read_bool(np, "is_master"); | ||
52 | |||
53 | /* Check that we are in dGPU mode */ | ||
54 | if (local_dev_id != NVLINK_ENDPT_GV100) { | ||
55 | nvgpu_err(g, "Local nvlink device is not dGPU"); | ||
56 | return -EINVAL; | ||
57 | } | ||
58 | |||
59 | ndev->is_master = is_master; | ||
60 | ndev->device_id = local_dev_id; | ||
61 | ndev->link.link_id = local_link_id; | ||
62 | ndev->link.remote_dev_info.device_id = remote_dev_id; | ||
63 | ndev->link.remote_dev_info.link_id = remote_link_id; | ||
64 | |||
65 | return 0; | ||
66 | |||
67 | fail: | ||
68 | nvgpu_info(g, "nvlink endpoint not found or invaling in DT"); | ||
69 | return -ENODEV; | ||
70 | } | ||
71 | #endif /* CONFIG_TEGRA_NVLINK */ | ||
72 | |||
73 | void nvgpu_mss_nvlink_init_credits(struct gk20a *g) | ||
74 | { | ||
75 | /* MSS_NVLINK_1_BASE */ | ||
76 | void __iomem *soc1 = ioremap(0x01f20010, 4096); | ||
77 | /* MSS_NVLINK_2_BASE */ | ||
78 | void __iomem *soc2 = ioremap(0x01f40010, 4096); | ||
79 | /* MSS_NVLINK_3_BASE */ | ||
80 | void __iomem *soc3 = ioremap(0x01f60010, 4096); | ||
81 | /* MSS_NVLINK_4_BASE */ | ||
82 | void __iomem *soc4 = ioremap(0x01f80010, 4096); | ||
83 | u32 val; | ||
84 | |||
85 | nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits"); | ||
86 | |||
87 | val = readl_relaxed(soc1); | ||
88 | writel_relaxed(val, soc1); | ||
89 | val = readl_relaxed(soc1 + 4); | ||
90 | writel_relaxed(val, soc1 + 4); | ||
91 | |||
92 | val = readl_relaxed(soc2); | ||
93 | writel_relaxed(val, soc2); | ||
94 | val = readl_relaxed(soc2 + 4); | ||
95 | writel_relaxed(val, soc2 + 4); | ||
96 | |||
97 | val = readl_relaxed(soc3); | ||
98 | writel_relaxed(val, soc3); | ||
99 | val = readl_relaxed(soc3 + 4); | ||
100 | writel_relaxed(val, soc3 + 4); | ||
101 | |||
102 | val = readl_relaxed(soc4); | ||
103 | writel_relaxed(val, soc4); | ||
104 | val = readl_relaxed(soc4 + 4); | ||
105 | writel_relaxed(val, soc4 + 4); | ||
106 | } | ||