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authorAlex Waterman <alexw@nvidia.com>2017-10-25 12:41:52 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-27 17:45:58 -0400
commit3fdb6d2e31389db65a71cad25ba907a1306e052b (patch)
treefdca69b5b2254a9183081a707a42105115a298b4 /drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
parent7974ad17bb7f389e5634bde58a91304918097495 (diff)
gpu: nvgpu: Remove Linux headers from mm_gk20a.h
Delte the Linux headers and make some modifications to get rid of the minor compilation issues that resulted. - Add <linux/iommu.h> to os_linux.h - Delete #if 0 code that "flushed" a buffer in gr_gk20a.c - Delete FLUSH_CPU_DCACHE() macro - Move the cache flush definitions to <nvgpu/linux/vm.h> and include this header in sim_gk20a.c. This file will not be used by QNX so this should be fine. - Add <linux/pci_ids.h> to gp106/bios_gp106.c and gp106/mclk_gp106.c. - Move function to common/linux/dmabuf.h since it is a dmabuf related function and uses a struct device pointer as an argument. JIRA NVGPU-30 Change-Id: I11f56b98524c7fac3efa91b4686592130e5f8a46 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585510 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
index 6c9fc26f..1e5a9d59 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
@@ -43,6 +43,7 @@
43#include "gk20a/fence_gk20a.h" 43#include "gk20a/fence_gk20a.h"
44 44
45#include "os_linux.h" 45#include "os_linux.h"
46#include "dmabuf.h"
46 47
47#define HZ_TO_MHZ(a) ((a > 0xF414F9CD7ULL) ? 0xffff : (a >> 32) ? \ 48#define HZ_TO_MHZ(a) ((a > 0xF414F9CD7ULL) ? 0xffff : (a >> 32) ? \
48 (u32) ((a * 0x10C8ULL) >> 32) : (u16) ((u32) a/MHZ)) 49 (u32) ((a * 0x10C8ULL) >> 32) : (u16) ((u32) a/MHZ))