diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 15:59:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-06-15 20:47:31 -0400 |
commit | 2a2c16af5f9f1ccfc93a13e820d5381e5c881e92 (patch) | |
tree | 2e5d7b042270a649978e5bb540857012c85fb5b5 /drivers/gpu/nvgpu/common/linux/fuse.c | |
parent | 98d996f4ffb0137d119b5849cae46d7b7e5693e1 (diff) |
gpu: nvgpu: Move Linux files away from common
Move all Linux source code files to drivers/gpu/nvgpu/os/linux from
drivers/gpu/nvgpu/common/linux. This changes the meaning of common
to be OS independent.
JIRA NVGPU-598
JIRA NVGPU-601
Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747714
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/fuse.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/fuse.c | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c deleted file mode 100644 index 27851f92..00000000 --- a/drivers/gpu/nvgpu/common/linux/fuse.c +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <soc/tegra/fuse.h> | ||
15 | |||
16 | #include <nvgpu/fuse.h> | ||
17 | |||
18 | int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g) | ||
19 | { | ||
20 | return tegra_sku_info.gpu_speedo_id; | ||
21 | } | ||
22 | |||
23 | /* | ||
24 | * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 | ||
25 | * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 | ||
26 | */ | ||
27 | void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val) | ||
28 | { | ||
29 | tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); | ||
30 | } | ||
31 | |||
32 | void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val) | ||
33 | { | ||
34 | tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); | ||
35 | } | ||
36 | |||
37 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val) | ||
38 | { | ||
39 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); | ||
40 | } | ||
41 | |||
42 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val) | ||
43 | { | ||
44 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); | ||
45 | } | ||
46 | |||
47 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val) | ||
48 | { | ||
49 | return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); | ||
50 | } | ||
51 | |||
52 | int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val) | ||
53 | { | ||
54 | return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); | ||
55 | } | ||