gpu: nvgpu: Set DMA mask to 34 bits

Set the DMA mask to 34 bits so that large DMA allocs can be done.
Currently the DMA mask is left unset which limits the size of the
maximum DMA allocation to 32 bits.

The 34 bit mask was chosen because it works for all chips (even
gm20b supports 34 bit physical addresses). However, newer chips
could use larger masks in the future if they desire.

Bug 200377221

Change-Id: Iaa0543f77ff4e2bd6616f38e4464240375bb37b6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1641762
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c
index 948bb69f..ed7f7fe9 100644
--- a/drivers/gpu/nvgpu/common/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/common/linux/driver_common.c
@@ -66,6 +66,10 @@ static void nvgpu_init_vars(struct gk20a *g)
         dev->dma_parms = &l->dma_parms;
         dma_set_max_seg_size(dev, UINT_MAX);
 
+        /* 34 bit mask - can be expanded for later chips is needed. */
+        dma_set_mask(dev, DMA_BIT_MASK(34));
+        dma_set_coherent_mask(dev, DMA_BIT_MASK(34));
+
         nvgpu_init_list_node(&g->pending_sema_waits);
         nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock);