gpu: nvgpu: gv11b: Correct PMU PG enabled masks.

PMU ucode records supported feature list for a
particular chip as support mask sent
via PMU_PG_PARAM_CMD_GR_INIT_PARAM.

It then enables selective feature list through
enable mask sent via
PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd.

Right now only ELPG state machine mask was enabled.
Only ELPG state machine was getting executed
but other crucial steps in ELPG entry/exit sequence
were getting skipped.

Bug 200392620.
Bug 200296076.

Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665767
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/debug_pmu.c b/drivers/gpu/nvgpu/common/linux/debug_pmu.c
index a8a8870e..f4ed992d 100644
--- a/drivers/gpu/nvgpu/common/linux/debug_pmu.c
+++ b/drivers/gpu/nvgpu/common/linux/debug_pmu.c
@@ -27,7 +27,7 @@ static int lpwr_debug_show(struct seq_file *s, void *data)
         if (g->ops.pmu.pmu_pg_engines_feature_list &&
                 g->ops.pmu.pmu_pg_engines_feature_list(g,
                 PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
-                PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
+                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
                 seq_printf(s, "PSTATE: %u\n"
                         "RPPG Enabled: %u\n"
                         "RPPG ref count: %u\n"