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authorAlex Frid <afrid@nvidia.com>2018-05-08 21:58:22 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-11 18:34:37 -0400
commit7a28547892bfa73d31c1423b33e98030840a4f6d (patch)
tree0c9f8c8dac79434d653a68ca933d2b3df750a779 /drivers/gpu/nvgpu/common/linux/clk.c
parent0732f4b83ee8f055155f25c876c870ff7d20ae99 (diff)
gpu: nvgpu: Fix Gpu sysfs access to Fmax@Vmin
Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS. In addition incorrect clock is used for DVFS information access. Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin read. This would fix a bug in target clock selection, and allows to remove dependency of sysfs on CONFIG_TEGRA_DVFS. Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be called on platforms that does not support Tegra DVFS, although 0 will still be returned as Fmax@Vmin on such platforms. Bug 2045903 Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1710924 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/clk.c')
-rw-r--r--drivers/gpu/nvgpu/common/linux/clk.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/clk.c b/drivers/gpu/nvgpu/common/linux/clk.c
index 8bffc07b..a0e56455 100644
--- a/drivers/gpu/nvgpu/common/linux/clk.c
+++ b/drivers/gpu/nvgpu/common/linux/clk.c
@@ -84,15 +84,18 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
84 return ret; 84 return ret;
85} 85}
86 86
87static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct clk_gk20a *clk) 87static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
88{ 88{
89 /* 89 /*
90 * On Tegra GPU clock exposed to frequency governor is a shared user on 90 * On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed
91 * GPCPLL bus (gbus). The latter can be accessed as GPU clock parent. 91 * to frequency governor is a shared user on the gbus. The latter can be
92 * Respectively the grandparent is PLL reference clock. 92 * accessed as GPU clock parent, and incorporate DVFS related data.
93 */ 93 */
94 return tegra_dvfs_get_fmax_at_vmin_safe_t( 94 if (g->clk.tegra_clk)
95 clk_get_parent(clk->tegra_clk)); 95 return tegra_dvfs_get_fmax_at_vmin_safe_t(
96 clk_get_parent(g->clk.tegra_clk));
97
98 return 0;
96} 99}
97 100
98static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g) 101static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g)