gpu: nvgpu: read GPC mask from h/w

In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate
GPC mask in s/w and return to user space
But this could give incorrect result as any GPC could be floorswept
in h/w

Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status
from fuse
Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w

Set these HALs only for dGPUs right now. Fuse register to read GPC
mask is not yet supported in simulation and hence simulation boot fails
These HALs will be set for iGPU once simulation issue is resolved

Use gops.gr.get_gpc_mask() if it is defined in
gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask
to user space

Jira NVGPUT-132

Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822811
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 6 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
index bb99e644..0dba3542 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
@@ -106,6 +106,11 @@ u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
         return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
 }
 
+u32 gm20b_fuse_status_opt_gpc(struct gk20a *g)
+{
+        return nvgpu_readl(g, fuse_status_opt_gpc_r());
+}
+
 u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
 {
         return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc));
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
index 5e2d194b..b22499ad 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
@@ -36,6 +36,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g);
 u32 gm20b_fuse_status_opt_fbio(struct gk20a *g);
 u32 gm20b_fuse_status_opt_fbp(struct gk20a *g);
 u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
+u32 gm20b_fuse_status_opt_gpc(struct gk20a *g);
 u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
 void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
 u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);