gpu: nvgpu: common: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I18cf871f2d1296b931d6ab43f1ac668551171dcc
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805076
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 6 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
index c790e297..bb99e644 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
@@ -63,16 +63,17 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
                          GCPLEX_CONFIG_WPR_ENABLED_MASK) &&
                         !(gcplex_config &
                                 GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) {
-                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r()))
+                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR debug",
                                                 gcplex_config);
-                        else
+                        } else {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR non debug",
                                                 gcplex_config);
+                        }
                 } else {
                         nvgpu_err(g, "gcplex_config = 0x%08x "
                                 "invalid wpr_enabled/vpr_auto_fetch_disable "
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
index 3a26e1b9..97570f9c 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
@@ -63,16 +63,17 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
                          GCPLEX_CONFIG_WPR_ENABLED_MASK) &&
                         !(gcplex_config &
                                 GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) {
-                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r()))
+                        if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR debug",
                                                 gcplex_config);
-                        else
+                        } else {
                                 nvgpu_log(g, gpu_dbg_info,
                                                 "gcplex_config = 0x%08x, "
                                                 "secure mode: ACR non debug",
                                                 gcplex_config);
+                        }
 
                 } else {
                         nvgpu_err(g, "gcplex_config = 0x%08x "