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authorsmadhavan <smadhavan@nvidia.com>2018-09-14 00:51:53 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-25 00:17:39 -0400
commit75e59e40045c6fbf93c5b828d8a12ba84b573585 (patch)
tree849405a26ee469bad7914882027ee4d2bce4bbc9 /drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
parentf93565c51fb465aebc34dc52fd704ba038c917f7 (diff)
nvgpu: common: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in common directory by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Idf10f6b179cfd96bfb8ab8e9e2bf79c26591905d Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809086 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/fuse/fuse_gp106.h')
-rw-r--r--drivers/gpu/nvgpu/common/fuse/fuse_gp106.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
index f014ee8c..24be7982 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP106 FUSE 2 * GP106 FUSE
3 * 3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#ifndef _NVGPU_GP106_FUSE 25#ifndef NVGPU_FUSE_GP106_H
26#define _NVGPU_GP106_FUSE 26#define NVGPU_FUSE_GP106_H
27 27
28struct gk20a; 28struct gk20a;
29 29
@@ -36,4 +36,4 @@ u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
36 u32 vin_id, s8 *gain, 36 u32 vin_id, s8 *gain,
37 s8 *offset); 37 s8 *offset);
38 38
39#endif 39#endif /* NVGPU_FUSE_GP106_H */