gpu: nvgpu: add refcounting for MMU debug mode

GPC MMU debug mode should be set if at least one channel
in the TSG has requested it. Add refcounting for MMU debug
mode, to make sure debug mode is disabled only when no
channel in the TSG is using it.

Bug 2515097
Bug 2713590

Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123017
(cherry picked from commit a1248d87fe6e20aab3e5f2e0764f9fe8d80d0552)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208769
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 47 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index 6d6c322e..5883667f 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -445,3 +445,49 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg,
         tsg_sm_error_states->hww_warp_esr_report_mask =
                         sm_error_state->hww_warp_esr_report_mask;
 }
+
+int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg,
+                struct channel_gk20a *ch, bool enable)
+{
+        struct gk20a *g;
+        int err = 0;
+        u32 tsg_refcnt;
+
+        if ((ch == NULL) || (tsg == NULL)) {
+                return -EINVAL;
+        }
+        g = ch->g;
+
+        if (g->ops.gr.set_mmu_debug_mode == NULL) {
+                return -ENOSYS;
+        }
+
+        if (enable) {
+                if (ch->mmu_debug_mode_enabled) {
+                        /* already enabled for this channel */
+                        return 0;
+                }
+                tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U;
+        } else {
+                if (!ch->mmu_debug_mode_enabled) {
+                        /* already disabled for this channel */
+                        return 0;
+                }
+                tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U;
+        }
+
+        /*
+         * enable GPC MMU debug mode if it was requested for at
+         * least one channel in the TSG
+         */
+        err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U);
+        if (err != 0) {
+                nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
+                return err;
+        }
+
+        ch->mmu_debug_mode_enabled = enable;
+        tsg->mmu_debug_mode_refcnt = tsg_refcnt;
+
+        return err;
+}