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| author | Scott Long <scottl@nvidia.com> | 2018-08-23 13:55:04 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-30 23:11:22 -0400 |
| commit | bc6625b9b2a2e5ef05cedf0888c28819d3c3f412 (patch) | |
| tree | ab2dad9f15885ff4b3ae698ea457d4b6d6eed4fc /drivers/gpu/nvgpu/common/fifo/channel.c | |
| parent | cded55940e6a8d616ef9cc62cacb537a7a2ef55a (diff) | |
gpu: nvgpu: fix zbc MISRA 10.1 violations
The gr_gk20a_add_zbc() routine returns a signed error
(errno) status value.
Current callers of this function use a bitwise OR to collect
the returned error status values to generate a single value
to return.
Bitwise OR on signed status values is flagged as a
violation of MISRA Rule 10.1 (not to mention that in this
case it potentially results in a garbage return value).
To eliminate such violations this change modifies the
following routines to fail immediately on the first error
from a call to gr_gk20a_add_zbc():
* gr_gk20a_load_zbc_default_table()
* gr_gv11b_load_stencil_default_tbl()
JIRA NVGPU-650
Change-Id: If733c1bb0e05943ff5d0355de729133c89233583
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805501
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/fifo/channel.c')
0 files changed, 0 insertions, 0 deletions