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authorTejal Kudav <tkudav@nvidia.com>2018-08-29 02:20:02 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-31 10:34:22 -0400
commit4940f4c1b44077849d1c3bbc63edcbc8c6d07480 (patch)
tree76f2b9781fe1134005487615274e4b2c81a5210f /drivers/gpu/nvgpu/common/fb/fb_gv100.c
parent0ba14d89a6c5ddf1af254e48c7ebad2ccf359a94 (diff)
gpu: nvgpu: Set nvdec mailbox reg 0 to nonzero val
The scrubber binary after completion updates its return code in mailbox register 0. The memory unlock code reads this registers to determine the success of memory scrubbing. This register is initialized to 0 during nvdec falcon reset. If the scrubber binary halts due to an error condition, the return code is not updated and it stays at 0. Initialize the status register explicitly to non-zero value helps avoid just false positives. Add falcon register dump and PC trace to help debug the memory unlock failures. Change-Id: I3086dda2a9719c2d0b8a7ae898f1a03bedfa21b0 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808899 Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/fb/fb_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gv100.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c
index d092ff4a..ce51a2c6 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c
@@ -192,6 +192,11 @@ int gv100_fb_memory_unlock(struct gk20a *g)
192 mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2], 192 mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2],
193 mem_unlock_ucode_header[OS_DATA_SIZE], 0); 193 mem_unlock_ucode_header[OS_DATA_SIZE], 0);
194 194
195 /* Write non-zero value to mailbox register which is updated by
196 * mem_unlock bin to denote its return status.
197 */
198 nvgpu_flcn_mailbox_write(&g->nvdec_flcn, 0, 0xdeadbeef);
199
195 /* set BOOTVEC to start of non-secure code */ 200 /* set BOOTVEC to start of non-secure code */
196 nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0); 201 nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0);
197 202
@@ -202,6 +207,7 @@ int gv100_fb_memory_unlock(struct gk20a *g)
202 val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0); 207 val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0);
203 if (val) { 208 if (val) {
204 nvgpu_err(g, "memory unlock failed, err %x", val); 209 nvgpu_err(g, "memory unlock failed, err %x", val);
210 nvgpu_flcn_dump_stats(&g->nvdec_flcn);
205 err = -1; 211 err = -1;
206 goto exit; 212 goto exit;
207 } 213 }