gpu: nvgpu: common: Fix MISRA 15.6 violations

This fixes errors due to single statement loop bodies
 without braces, which is part of Rule 15.6 of MISRA.
 This patch covers in gpu/nvgpu/common/

JIRA NVGPU-989

Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786207
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index 8e37a709..048bb760 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -284,10 +284,11 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src,
                         break;
                 }
 
-                for (i = 0; i < (byte_read_count >> 2); i += 4)
+                for (i = 0; i < (byte_read_count >> 2); i += 4) {
                         nvgpu_info(flcn->g, "%#06x: %#010x %#010x %#010x %#010x",
-                        src + (i << 2), buff[i], buff[i+1],
-                        buff[i+2], buff[i+3]);
+                                src + (i << 2), buff[i], buff[i+1],
+                                buff[i+2], buff[i+3]);
+                }
 
                 src += byte_read_count;
                 size -= byte_read_count;