gpu: nvgpu: SEC2 RTOS support s/w init

-Created struct nvgpu_sec2 to hold members
 related to SEC2-RTOS ucode support in header file
 sec2.h
-Created nvgpu_sec2 variable under struct gk20a.
-Created NVGPU_SUPPORT_SEC2_RTOS enable flag
 to enable SEC2 RTOS support.
-Defined method nvgpu_init_sec2_support() to
 init SEC2 RTOS support by performing s/w setup like
 mutex-init, sequence-init & add support
 for remove_support.
-Defined method nvgpu_sec2_destroy() to deinit
 SEC2 RTOS support.
-Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy()
 as part gk20a_finalize_poweron()/gk20a_prepare_poweroff()
 sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag
-Assigned g->sec2->flcn to point to g->sec2_flcn to access
 falcon.
-Made Makefile changes to include sec2.c to build

JIRA NVGPUT-80

Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791955
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index b1d6558a..451b8450 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -440,6 +440,8 @@ int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id)
         case FALCON_ID_SEC2:
                 flcn = &g->sec2_flcn;
                 flcn->flcn_id = flcn_id;
+                g->sec2.flcn = &g->sec2_flcn;
+                g->sec2.g = g;
                 break;
         case FALCON_ID_FECS:
                 flcn = &g->fecs_flcn;