diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-06-27 12:23:51 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-21 20:34:28 -0400 |
commit | 1cee7b2a390a8b2486b25d2383e4e11667dcff08 (patch) | |
tree | 16ca6411a6d17f42ed8063a8298bd42e8df9b018 /drivers/gpu/nvgpu/common/falcon | |
parent | 50a1cc069a6b28757de1af1617c0f9f037b60c6a (diff) |
gpu: nvgpu: falcon interface/HAL update
- Add methods to read/write falcon mailbox
at interface layer
- Created falcon mailbox read/write HAL
- Added HAL methods to read/write mailbox
- Added macro to get next block based on address
- Added macro to get IMEM tag using IMEM address
- Added ucode header format
Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63)
Reviewed-on: https://git-master.nvidia.com/r/1509469
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/falcon')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 99b2c249..d8420ece 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -286,6 +286,32 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) | |||
286 | return status; | 286 | return status; |
287 | } | 287 | } |
288 | 288 | ||
289 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index) | ||
290 | { | ||
291 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
292 | u32 data = 0; | ||
293 | |||
294 | if (flcn_ops->mailbox_read) | ||
295 | data = flcn_ops->mailbox_read(flcn, mailbox_index); | ||
296 | else | ||
297 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
298 | flcn->flcn_id); | ||
299 | |||
300 | return data; | ||
301 | } | ||
302 | |||
303 | void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, | ||
304 | u32 data) | ||
305 | { | ||
306 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
307 | |||
308 | if (flcn_ops->mailbox_write) | ||
309 | flcn_ops->mailbox_write(flcn, mailbox_index, data); | ||
310 | else | ||
311 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
312 | flcn->flcn_id); | ||
313 | } | ||
314 | |||
289 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) | 315 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) |
290 | { | 316 | { |
291 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | 317 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; |