gpu: nvgpu: common: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I599cce2af1d6cdc24efefba4ec42abfe998aec47
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795845
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 52 insertions, 31 deletions

diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index 41dca0cd..81ba5e81 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -50,12 +50,14 @@ int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn)
         do {
                 idle_stat = flcn_ops->is_falcon_idle(flcn);
 
-                if (idle_stat)
+                if (idle_stat) {
                         break;
+                }
 
                 if (nvgpu_timeout_expired_msg(&timeout,
-                        "waiting for falcon idle: 0x%08x", idle_stat))
+                        "waiting for falcon idle: 0x%08x", idle_stat)) {
                         return -EBUSY;
+                }
 
                 nvgpu_usleep_range(100, 200);
         } while (1);
@@ -74,13 +76,15 @@ int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn)
                 MEM_SCRUBBING_TIMEOUT_DEFAULT,
                 NVGPU_TIMER_RETRY_TIMER);
         do {
-                if (nvgpu_flcn_get_mem_scrubbing_status(flcn))
+                if (nvgpu_flcn_get_mem_scrubbing_status(flcn)) {
                         goto exit;
+                }
                 nvgpu_udelay(MEM_SCRUBBING_TIMEOUT_DEFAULT);
         } while (!nvgpu_timeout_expired(&timeout));
 
-        if (nvgpu_timeout_peek_expired(&timeout))
+        if (nvgpu_timeout_peek_expired(&timeout)) {
                 status = -ETIMEDOUT;
+        }
 
 exit:
         return status;
@@ -92,8 +96,9 @@ int nvgpu_flcn_reset(struct nvgpu_falcon *flcn)
 
         if (flcn->flcn_ops.reset) {
                 status = flcn->flcn_ops.reset(flcn);
-                if (!status)
+                if (!status) {
                         status = nvgpu_flcn_mem_scrub_wait(flcn);
+                }
         } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
@@ -112,9 +117,10 @@ void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable,
                 flcn->intr_mask = intr_mask;
                 flcn->intr_dest = intr_dest;
                 flcn_ops->set_irq(flcn, enable);
-        } else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 }
 
 bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn)
@@ -122,11 +128,12 @@ bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn)
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         bool status = false;
 
-        if (flcn_ops->is_falcon_scrubbing_done)
+        if (flcn_ops->is_falcon_scrubbing_done) {
                 status = flcn_ops->is_falcon_scrubbing_done(flcn);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return status;
 }
@@ -136,11 +143,12 @@ bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn)
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         bool status = false;
 
-        if (flcn_ops->is_falcon_cpu_halted)
+        if (flcn_ops->is_falcon_cpu_halted) {
                 status = flcn_ops->is_falcon_cpu_halted(flcn);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return status;
 }
@@ -153,14 +161,16 @@ int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout)
 
         nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER);
         do {
-                if (nvgpu_flcn_get_cpu_halted_status(flcn))
+                if (nvgpu_flcn_get_cpu_halted_status(flcn)) {
                         break;
+                }
 
                 nvgpu_udelay(10);
         } while (!nvgpu_timeout_expired(&to));
 
-        if (nvgpu_timeout_peek_expired(&to))
+        if (nvgpu_timeout_peek_expired(&to)) {
                 status = -EBUSY;
+        }
 
         return status;
 }
@@ -181,14 +191,16 @@ int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn,
 
         nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER);
         do {
-                if (flcn_ops->clear_halt_interrupt_status(flcn))
+                if (flcn_ops->clear_halt_interrupt_status(flcn)) {
                         break;
+                }
 
                 nvgpu_udelay(1);
         } while (!nvgpu_timeout_expired(&to));
 
-        if (nvgpu_timeout_peek_expired(&to))
+        if (nvgpu_timeout_peek_expired(&to)) {
                 status = -EBUSY;
+        }
 
         return status;
 }
@@ -198,11 +210,12 @@ bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn)
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         bool status = false;
 
-        if (flcn_ops->is_falcon_idle)
+        if (flcn_ops->is_falcon_idle) {
                 status = flcn_ops->is_falcon_idle(flcn);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return status;
 }
@@ -229,11 +242,12 @@ int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn,
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         int status = -EINVAL;
 
-        if (flcn_ops->copy_from_imem)
+        if (flcn_ops->copy_from_imem) {
                 status = flcn_ops->copy_from_imem(flcn, src, dst, size, port);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return status;
 }
@@ -244,12 +258,13 @@ int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn,
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         int status = -EINVAL;
 
-        if (flcn_ops->copy_to_imem)
+        if (flcn_ops->copy_to_imem) {
                 status = flcn_ops->copy_to_imem(flcn, dst, src, size, port,
                                         sec, tag);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return status;
 }
@@ -269,15 +284,17 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src,
         do {
                 byte_read_count = total_block_read ? sizeof(buff) : size;
 
-                if (!byte_read_count)
+                if (!byte_read_count) {
                         break;
+                }
 
-                if (mem_type == MEM_DMEM)
+                if (mem_type == MEM_DMEM) {
                         status = nvgpu_flcn_copy_from_dmem(flcn, src,
                                 (u8 *)buff, byte_read_count, 0);
-                else
+                } else {
                         status = nvgpu_flcn_copy_from_imem(flcn, src,
                                 (u8 *)buff, byte_read_count, 0);
+                }
 
                 if (status) {
                         nvgpu_err(flcn->g, "MEM print failed");
@@ -312,11 +329,12 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         int status = -EINVAL;
 
-        if (flcn_ops->bootstrap)
+        if (flcn_ops->bootstrap) {
                 status = flcn_ops->bootstrap(flcn, boot_vector);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return status;
 }
@@ -326,11 +344,12 @@ u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index)
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
         u32 data = 0;
 
-        if (flcn_ops->mailbox_read)
+        if (flcn_ops->mailbox_read) {
                 data = flcn_ops->mailbox_read(flcn, mailbox_index);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 
         return data;
 }
@@ -340,22 +359,24 @@ void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
 {
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
 
-        if (flcn_ops->mailbox_write)
+        if (flcn_ops->mailbox_write) {
                 flcn_ops->mailbox_write(flcn, mailbox_index, data);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 }
 
 void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn)
 {
         struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
 
-        if (flcn_ops->dump_falcon_stats)
+        if (flcn_ops->dump_falcon_stats) {
                 flcn_ops->dump_falcon_stats(flcn);
-        else
+        } else {
                 nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
                         flcn->flcn_id);
+        }
 }
 
 int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn,