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| author | Peter Daifuku <pdaifuku@nvidia.com> | 2020-09-30 14:25:05 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-10-06 13:10:02 -0400 |
| commit | 5a948ccca95bcecf9d1e81db02394134f8a18c38 (patch) | |
| tree | fb9e43f6750d9c804e5eb8b161a1c634428f9914 /drivers/gpu/nvgpu/common/clock_gating | |
| parent | cd134bb198d7138a3c2fcb17d11f2eedf934e2c4 (diff) | |
gpu: nvgpu: limit PD cache to < pgsize for linux
For Linux, limit the use of the cache to entries less than the page size, to
avoid potential problems with running out of CMA memory when allocating large,
contiguous slabs, as would be required for non-iommmuable chips.
Also, in nvgpu_pd_cache_do_free(), zero out entries only if iommu is in use
and PTE entries use the cache (since it's the prefetch of invalid PTEs by
iommu that needs to be avoided).
Bug 3093183
Bug 3100907
Change-Id: I363031db32e11bc705810a7e87fc9e9ac1dc00bd
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422039
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Satish Arora <satisha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/clock_gating')
0 files changed, 0 insertions, 0 deletions