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authorVinod G <vinodg@nvidia.com>2018-05-18 19:38:55 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-24 07:38:06 -0400
commit0f81c5616b04dea9772f490636d0a1959a42774e (patch)
tree6272bffd42d076d14739843fd50ec12ab582029b /drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c
parentd9128f697c41a61c02fa7511ecb1f8bbf0e081a2 (diff)
gpu: nvgpu: Code updates for MISRA violations
Regenerated the gating_reglist.c files for various chips after fixing the script for MISRA C-2012 violations Rule 15.5: Multiple points of exit detected Rule 15.6: "if" body without compound statement Rule 10.3: Implicit conversions of 64bit to 32bit int Rule 7.2: Const must be declared with "U" Rule 5.7: Tags with name xxx already declared Add preprocessor conditional gaurds in gating_reglist header files JIRA NVGPU-671 JIRA NVGPU-656 JIRA NVGPU-688 JIRA NVGPU-686 JIRA NVGPU-644 Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724444 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c1214
1 files changed, 570 insertions, 644 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c
index 18703a23..8624f633 100644
--- a/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c
+++ b/drivers/gpu/nvgpu/common/clock_gating/gv100_gating_reglist.c
@@ -18,269 +18,268 @@
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 *
21 * This file is autogenerated. Do not edit. 22 * This file is autogenerated. Do not edit.
22 */ 23 */
23 24
24#ifndef __gv100_gating_reglist_h__
25#define __gv100_gating_reglist_h__
26
27#include <nvgpu/types.h> 25#include <nvgpu/types.h>
26#include <nvgpu/io.h>
27#include <nvgpu/enabled.h>
28
29#include "gating_reglist.h"
28#include "gv100_gating_reglist.h" 30#include "gv100_gating_reglist.h"
29 31
30struct gating_desc { 32#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
31 u32 addr; 33
32 u32 prod;
33 u32 disable;
34};
35/* slcg bus */ 34/* slcg bus */
36static const struct gating_desc gv100_slcg_bus[] = { 35static const struct gating_desc gv100_slcg_bus[] = {
37 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, 36 {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
38}; 37};
39 38
40/* slcg ce2 */ 39/* slcg ce2 */
41static const struct gating_desc gv100_slcg_ce2[] = { 40static const struct gating_desc gv100_slcg_ce2[] = {
42 {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, 41 {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU},
43}; 42};
44 43
45/* slcg chiplet */ 44/* slcg chiplet */
46static const struct gating_desc gv100_slcg_chiplet[] = { 45static const struct gating_desc gv100_slcg_chiplet[] = {
47 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, 46 {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
48 {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007}, 47 {.addr = 0x0010c17cU, .prod = 0x00000000U, .disable = 0x00000007U},
49 {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007}, 48 {.addr = 0x0010c27cU, .prod = 0x00000000U, .disable = 0x00000007U},
50 {.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007}, 49 {.addr = 0x0010c37cU, .prod = 0x00000000U, .disable = 0x00000007U},
51 {.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007}, 50 {.addr = 0x0010c47cU, .prod = 0x00000000U, .disable = 0x00000007U},
52 {.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007}, 51 {.addr = 0x0010c57cU, .prod = 0x00000000U, .disable = 0x00000007U},
53 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, 52 {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
54 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, 53 {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
55 {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007}, 54 {.addr = 0x0010d17cU, .prod = 0x00000000U, .disable = 0x00000007U},
56 {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007}, 55 {.addr = 0x0010d27cU, .prod = 0x00000000U, .disable = 0x00000007U},
57 {.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007}, 56 {.addr = 0x0010d37cU, .prod = 0x00000000U, .disable = 0x00000007U},
58 {.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007}, 57 {.addr = 0x0010d47cU, .prod = 0x00000000U, .disable = 0x00000007U},
59 {.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007}, 58 {.addr = 0x0010d57cU, .prod = 0x00000000U, .disable = 0x00000007U},
60 /* fix priv error */ 59 /* fix priv error */
61 /*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/ 60 /*{.addr = 0x0010d67cU, .prod = 0x00000000U, .disable = 0x00000007U},*/
62 /*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/ 61 /*{.addr = 0x0010d77cU, .prod = 0x00000000U, .disable = 0x00000007U},*/
63 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, 62 {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
64}; 63};
65 64
66/* slcg fb */ 65/* slcg fb */
67static const struct gating_desc gv100_slcg_fb[] = { 66static const struct gating_desc gv100_slcg_fb[] = {
68 {.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe}, 67 {.addr = 0x00100d14U, .prod = 0x00000020U, .disable = 0xfffffffeU},
69 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, 68 {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
70 {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, 69 {.addr = 0x001facb4U, .prod = 0x00000000U, .disable = 0x000001feU},
71}; 70};
72 71
73/* slcg fifo */ 72/* slcg fifo */
74static const struct gating_desc gv100_slcg_fifo[] = { 73static const struct gating_desc gv100_slcg_fifo[] = {
75 {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, 74 {.addr = 0x000026ecU, .prod = 0x00000000U, .disable = 0x0001fffeU},
76}; 75};
77 76
78/* slcg gr */ 77/* slcg gr */
79static const struct gating_desc gv100_slcg_gr[] = { 78static const struct gating_desc gv100_slcg_gr[] = {
80 {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, 79 {.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x07fffffeU},
81 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, 80 {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
82 {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, 81 {.addr = 0x00409894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
83 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, 82 {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
84 {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, 83 {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU},
85 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, 84 {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
86 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, 85 {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
87 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, 86 {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
88 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, 87 {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},
89 {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, 88 {.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U},
90 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, 89 {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
91 {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, 90 {.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
92 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, 91 {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
93 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, 92 {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
94 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, 93 {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
95 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, 94 {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU},
96 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, 95 {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
97 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, 96 {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
98 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, 97 {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
99 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, 98 {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
100 {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, 99 {.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU},
101 {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, 100 {.addr = 0x00418cf4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
102 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, 101 {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
103 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, 102 {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
104 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, 103 {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
105 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, 104 {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
106 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, 105 {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
107 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, 106 {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU},
108 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, 107 {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
109 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, 108 {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
110 /* fix priv error */ 109 /* fix priv error */
111 /*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/ 110 /*{.addr = 0x00419c84U, .prod = 0x0003fffeU, .disable = 0x0003fffeU},*/
112 {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, 111 {.addr = 0x00419c8cU, .prod = 0xffffff84U, .disable = 0xfffffffeU},
113 {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, 112 {.addr = 0x00419c94U, .prod = 0x00000240U, .disable = 0x00007ffeU},
114 {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, 113 {.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU},
115 {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, 114 {.addr = 0x00419cacU, .prod = 0x0001fffeU, .disable = 0x0001fffeU},
116 {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, 115 {.addr = 0x00419a44U, .prod = 0x00000008U, .disable = 0x0000000eU},
117 {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, 116 {.addr = 0x00419a4cU, .prod = 0x000001f8U, .disable = 0x000001feU},
118 {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, 117 {.addr = 0x00419a54U, .prod = 0x0000003cU, .disable = 0x0000003eU},
119 {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, 118 {.addr = 0x00419a5cU, .prod = 0x0000000cU, .disable = 0x0000000eU},
120 {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, 119 {.addr = 0x00419a64U, .prod = 0x00000186U, .disable = 0x000001feU},
121 {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, 120 {.addr = 0x00419a7cU, .prod = 0x0000003cU, .disable = 0x0000003eU},
122 {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, 121 {.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU},
123 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, 122 {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
124 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, 123 {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
125 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, 124 {.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
126 {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe}, 125 {.addr = 0x00412814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
127 {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe}, 126 {.addr = 0x00412a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
128 {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe}, 127 {.addr = 0x004129acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
129 {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff}, 128 {.addr = 0x00412a24U, .prod = 0x00000000U, .disable = 0x000000ffU},
130 {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe}, 129 {.addr = 0x00412c14U, .prod = 0x00000000U, .disable = 0x0001fffeU},
131 {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe}, 130 {.addr = 0x00412e84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
132 {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe}, 131 {.addr = 0x00412dacU, .prod = 0x00000000U, .disable = 0x0001fffeU},
133 {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff}, 132 {.addr = 0x00412e24U, .prod = 0x00000000U, .disable = 0x000000ffU},
134 /* fix priv error */ 133 /* fix priv error */
135 /*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/ 134 /*{.addr = 0x00413014U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
136 /*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/ 135 /*{.addr = 0x00413284U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
137 /*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ 136 /*{.addr = 0x004131acU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
138 /*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/ 137 /*{.addr = 0x00413224U, .prod = 0x00000000U, .disable = 0x000000ffU},*/
139 /*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/ 138 /*{.addr = 0x00413414U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
140 /*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/ 139 /*{.addr = 0x00413684U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
141 /*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ 140 /*{.addr = 0x004135acU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
142 /*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/ 141 /*{.addr = 0x00413624U, .prod = 0x00000000U, .disable = 0x000000ffU},*/
143 /*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/ 142 /*{.addr = 0x00413814U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
144 /*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/ 143 /*{.addr = 0x00413a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
145 /*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/ 144 /*{.addr = 0x004139acU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
146 /*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/ 145 /*{.addr = 0x00413a24U, .prod = 0x00000000U, .disable = 0x000000ffU},*/
147 /*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/ 146 /*{.addr = 0x00413c14U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
148 /*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/ 147 /*{.addr = 0x00413e84U, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
149 /*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/ 148 /*{.addr = 0x00413dacU, .prod = 0x00000000U, .disable = 0x0001fffeU},*/
150 /*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/ 149 /*{.addr = 0x00413e24U, .prod = 0x00000000U, .disable = 0x000000ffU},*/
151 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, 150 {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
152 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, 151 {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
153 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, 152 {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
154 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, 153 {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000000ffU},
155}; 154};
156 155
157/* slcg ltc */ 156/* slcg ltc */
158static const struct gating_desc gv100_slcg_ltc[] = { 157static const struct gating_desc gv100_slcg_ltc[] = {
159 {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe}, 158 {.addr = 0x00154050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
160 {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe}, 159 {.addr = 0x0015455cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
161 {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe}, 160 {.addr = 0x0015475cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
162 {.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe}, 161 {.addr = 0x0015495cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
163 {.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe}, 162 {.addr = 0x00154b5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
164 {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe}, 163 {.addr = 0x0015435cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
165 {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe}, 164 {.addr = 0x00156050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
166 {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe}, 165 {.addr = 0x0015655cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
167 {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe}, 166 {.addr = 0x0015675cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
168 {.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe}, 167 {.addr = 0x0015695cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
169 {.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe}, 168 {.addr = 0x00156b5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
170 {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe}, 169 {.addr = 0x0015635cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
171 /* fix priv error */ 170 /* fix priv error */
172 /*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/ 171 /*{.addr = 0x00158050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
173 /*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 172 /*{.addr = 0x0015855cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
174 /*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 173 /*{.addr = 0x0015875cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
175 /*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 174 /*{.addr = 0x0015895cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
176 /*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 175 /*{.addr = 0x00158b5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
177 /*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 176 /*{.addr = 0x0015835cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
178 /*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/ 177 /*{.addr = 0x0015a050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
179 /*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 178 /*{.addr = 0x0015a55cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
180 /*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 179 /*{.addr = 0x0015a75cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
181 /*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 180 /*{.addr = 0x0015a95cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
182 /*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 181 /*{.addr = 0x0015ab5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
183 /*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 182 /*{.addr = 0x0015a35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
184 /*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/ 183 /*{.addr = 0x0015c050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
185 /*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 184 /*{.addr = 0x0015c55cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
186 /*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 185 /*{.addr = 0x0015c75cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
187 /*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 186 /*{.addr = 0x0015c95cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
188 /*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 187 /*{.addr = 0x0015cb5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
189 /*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 188 /*{.addr = 0x0015c35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
190 /*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/ 189 /*{.addr = 0x0015e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
191 /*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 190 /*{.addr = 0x0015e55cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
192 /*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 191 /*{.addr = 0x0015e75cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
193 /*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 192 /*{.addr = 0x0015e95cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
194 /*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 193 /*{.addr = 0x0015eb5cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
195 /*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/ 194 /*{.addr = 0x0015e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},*/
196 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, 195 {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
197 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, 196 {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
198}; 197};
199 198
200/* slcg perf */ 199/* slcg perf */
201static const struct gating_desc gv100_slcg_perf[] = { 200static const struct gating_desc gv100_slcg_perf[] = {
202 {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, 201 {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U},
203 {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, 202 {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U},
204 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, 203 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
205 {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, 204 {.addr = 0x00246218U, .prod = 0xffffffffU, .disable = 0x00000000U},
206 {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, 205 {.addr = 0x00246418U, .prod = 0xffffffffU, .disable = 0x00000000U},
207 {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, 206 {.addr = 0x00246618U, .prod = 0xffffffffU, .disable = 0x00000000U},
208 {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, 207 {.addr = 0x00246818U, .prod = 0xffffffffU, .disable = 0x00000000U},
209 {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, 208 {.addr = 0x00246a18U, .prod = 0xffffffffU, .disable = 0x00000000U},
210 /* fix priv error */ 209 /* fix priv error */
211 /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ 210 /*{.addr = 0x00246c18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/
212 /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ 211 /*{.addr = 0x00246e18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/
213 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, 212 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
214 {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000}, 213 {.addr = 0x00246218U, .prod = 0xffffffffU, .disable = 0x00000000U},
215 {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000}, 214 {.addr = 0x00246418U, .prod = 0xffffffffU, .disable = 0x00000000U},
216 {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000}, 215 {.addr = 0x00246618U, .prod = 0xffffffffU, .disable = 0x00000000U},
217 {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000}, 216 {.addr = 0x00246818U, .prod = 0xffffffffU, .disable = 0x00000000U},
218 {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000}, 217 {.addr = 0x00246a18U, .prod = 0xffffffffU, .disable = 0x00000000U},
219 /* fix priv error */ 218 /* fix priv error */
220 /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/ 219 /*{.addr = 0x00246c18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/
221 /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/ 220 /*{.addr = 0x00246e18U, .prod = 0xffffffffU, .disable = 0x00000000U},*/
222 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, 221 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
223 {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, 222 {.addr = 0x00244218U, .prod = 0xffffffffU, .disable = 0x00000000U},
224 {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, 223 {.addr = 0x00244418U, .prod = 0xffffffffU, .disable = 0x00000000U},
225 {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, 224 {.addr = 0x00244618U, .prod = 0xffffffffU, .disable = 0x00000000U},
226 {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, 225 {.addr = 0x00244818U, .prod = 0xffffffffU, .disable = 0x00000000U},
227 {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, 226 {.addr = 0x00244a18U, .prod = 0xffffffffU, .disable = 0x00000000U},
228 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, 227 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
229 {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000}, 228 {.addr = 0x00244218U, .prod = 0xffffffffU, .disable = 0x00000000U},
230 {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000}, 229 {.addr = 0x00244418U, .prod = 0xffffffffU, .disable = 0x00000000U},
231 {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000}, 230 {.addr = 0x00244618U, .prod = 0xffffffffU, .disable = 0x00000000U},
232 {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000}, 231 {.addr = 0x00244818U, .prod = 0xffffffffU, .disable = 0x00000000U},
233 {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000}, 232 {.addr = 0x00244a18U, .prod = 0xffffffffU, .disable = 0x00000000U},
234 {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, 233 {.addr = 0x0024a124U, .prod = 0x00000001U, .disable = 0x00000000U},
235}; 234};
236 235
237/* slcg PriRing */ 236/* slcg PriRing */
238static const struct gating_desc gv100_slcg_priring[] = { 237static const struct gating_desc gv100_slcg_priring[] = {
239 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, 238 {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
240}; 239};
241 240
242/* slcg pwr_csb */ 241/* slcg pwr_csb */
243static const struct gating_desc gv100_slcg_pwr_csb[] = { 242static const struct gating_desc gv100_slcg_pwr_csb[] = {
244 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, 243 {.addr = 0x00000134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
245 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, 244 {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU},
246 {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, 245 {.addr = 0x00000a74U, .prod = 0x00000000U, .disable = 0x00007ffeU},
247 {.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f}, 246 {.addr = 0x000016b8U, .prod = 0x00000008U, .disable = 0x0000000fU},
248}; 247};
249 248
250/* slcg pmu */ 249/* slcg pmu */
251static const struct gating_desc gv100_slcg_pmu[] = { 250static const struct gating_desc gv100_slcg_pmu[] = {
252 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, 251 {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
253 {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, 252 {.addr = 0x0010aa74U, .prod = 0x00000000U, .disable = 0x00007ffeU},
254 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, 253 {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
255}; 254};
256 255
257/* therm gr */ 256/* therm gr */
258static const struct gating_desc gv100_slcg_therm[] = { 257static const struct gating_desc gv100_slcg_therm[] = {
259 {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, 258 {.addr = 0x000206b8U, .prod = 0x00000008U, .disable = 0x0000000fU},
260}; 259};
261 260
262/* slcg Xbar */ 261/* slcg Xbar */
263static const struct gating_desc gv100_slcg_xbar[] = { 262static const struct gating_desc gv100_slcg_xbar[] = {
264 {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, 263 {.addr = 0x0013c824U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
265 {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, 264 {.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU},
266 {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, 265 {.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
267 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, 266 {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
268 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, 267 {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
269 {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, 268 {.addr = 0x0013cc24U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
270 {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe}, 269 {.addr = 0x0013cc44U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
271 {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe}, 270 {.addr = 0x0013cc64U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
272 {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe}, 271 {.addr = 0x0013cc84U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
273 {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe}, 272 {.addr = 0x0013cca4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
274}; 273};
275 274
276/* blcg bus */ 275/* blcg bus */
277static const struct gating_desc gv100_blcg_bus[] = { 276static const struct gating_desc gv100_blcg_bus[] = {
278 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, 277 {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
279}; 278};
280 279
281/* blcg ce */ 280/* blcg ce */
282static const struct gating_desc gv100_blcg_ce[] = { 281static const struct gating_desc gv100_blcg_ce[] = {
283 {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, 282 {.addr = 0x00104200U, .prod = 0x0000c242U, .disable = 0x00000000U},
284}; 283};
285 284
286/* blcg ctxsw prog */ 285/* blcg ctxsw prog */
@@ -289,197 +288,196 @@ static const struct gating_desc gv100_blcg_ctxsw_prog[] = {
289 288
290/* blcg fb */ 289/* blcg fb */
291static const struct gating_desc gv100_blcg_fb[] = { 290static const struct gating_desc gv100_blcg_fb[] = {
292 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, 291 {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
293 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, 292 {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
294 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, 293 {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
295 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, 294 {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
296 /* fix priv error */ 295 {.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},
297 /*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/ 296 {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
298 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, 297 {.addr = 0x001facb0U, .prod = 0x00004242U, .disable = 0x00000000U},
299 {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000},
300}; 298};
301 299
302/* blcg fifo */ 300/* blcg fifo */
303static const struct gating_desc gv100_blcg_fifo[] = { 301static const struct gating_desc gv100_blcg_fifo[] = {
304 {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, 302 {.addr = 0x000026e0U, .prod = 0x0000c242U, .disable = 0x00000000U},
305}; 303};
306 304
307/* blcg gr */ 305/* blcg gr */
308static const struct gating_desc gv100_blcg_gr[] = { 306static const struct gating_desc gv100_blcg_gr[] = {
309 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, 307 {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
310 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, 308 {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
311 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, 309 {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
312 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, 310 {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
313 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, 311 {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
314 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, 312 {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
315 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, 313 {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
316 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, 314 {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U},
317 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, 315 {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
318 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, 316 {.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
319 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, 317 {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
320 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, 318 {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
321 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, 319 {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
322 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, 320 {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
323 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, 321 {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
324 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, 322 {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
325 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, 323 {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
326 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, 324 {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
327 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, 325 {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
328 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, 326 {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
329 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, 327 {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
330 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, 328 {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
331 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, 329 {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
332 {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, 330 {.addr = 0x00418e0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
333 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, 331 {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
334 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, 332 {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U},
335 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, 333 {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
336 {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, 334 {.addr = 0x00419868U, .prod = 0x00008243U, .disable = 0x00000000U},
337 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, 335 {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
338 {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, 336 {.addr = 0x00419c80U, .prod = 0x00004048U, .disable = 0x00000000U},
339 {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, 337 {.addr = 0x00419c88U, .prod = 0x00004048U, .disable = 0x00000000U},
340 {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, 338 {.addr = 0x00419c90U, .prod = 0x0000004aU, .disable = 0x00000000U},
341 {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, 339 {.addr = 0x00419c98U, .prod = 0x00000042U, .disable = 0x00000000U},
342 {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, 340 {.addr = 0x00419ca0U, .prod = 0x00000043U, .disable = 0x00000000U},
343 {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, 341 {.addr = 0x00419ca8U, .prod = 0x00000003U, .disable = 0x00000000U},
344 {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, 342 {.addr = 0x00419cb0U, .prod = 0x00000002U, .disable = 0x00000000U},
345 {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, 343 {.addr = 0x00419a40U, .prod = 0x00000545U, .disable = 0x00000000U},
346 {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, 344 {.addr = 0x00419a48U, .prod = 0x00004545U, .disable = 0x00000000U},
347 {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, 345 {.addr = 0x00419a50U, .prod = 0x00004545U, .disable = 0x00000000U},
348 {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, 346 {.addr = 0x00419a58U, .prod = 0x00004545U, .disable = 0x00000000U},
349 {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, 347 {.addr = 0x00419a60U, .prod = 0x00000505U, .disable = 0x00000000U},
350 {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, 348 {.addr = 0x00419a68U, .prod = 0x00000505U, .disable = 0x00000000U},
351 {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, 349 {.addr = 0x00419a78U, .prod = 0x00000505U, .disable = 0x00000000U},
352 {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, 350 {.addr = 0x00419a80U, .prod = 0x00004545U, .disable = 0x00000000U},
353 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, 351 {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
354 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, 352 {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
355 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, 353 {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
356 {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000}, 354 {.addr = 0x00412810U, .prod = 0x0000c242U, .disable = 0x00000000U},
357 {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000}, 355 {.addr = 0x00412a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
358 {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000}, 356 {.addr = 0x004129a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
359 {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000}, 357 {.addr = 0x00412c10U, .prod = 0x0000c242U, .disable = 0x00000000U},
360 {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000}, 358 {.addr = 0x00412e80U, .prod = 0x0000c242U, .disable = 0x00000000U},
361 {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000}, 359 {.addr = 0x00412da8U, .prod = 0x0000c242U, .disable = 0x00000000U},
362 /* fix priv error */ 360 /* fix priv error */
363 /*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/ 361 /*{.addr = 0x00413010U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
364 /*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/ 362 /*{.addr = 0x00413280U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
365 /*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/ 363 /*{.addr = 0x004131a8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
366 /*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/ 364 /*{.addr = 0x00413410U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
367 /*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/ 365 /*{.addr = 0x00413680U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
368 /*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/ 366 /*{.addr = 0x004135a8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
369 /*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/ 367 /*{.addr = 0x00413810U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
370 /*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/ 368 /*{.addr = 0x00413a80U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
371 /*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/ 369 /*{.addr = 0x004139a8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
372 /*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/ 370 /*{.addr = 0x00413c10U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
373 /*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/ 371 /*{.addr = 0x00413e80U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
374 /*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/ 372 /*{.addr = 0x00413da8U, .prod = 0x0000c242U, .disable = 0x00000000U},*/
375 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, 373 {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U},
376 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, 374 {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
377 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, 375 {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
378}; 376};
379 377
380/* blcg ltc */ 378/* blcg ltc */
381static const struct gating_desc gv100_blcg_ltc[] = { 379static const struct gating_desc gv100_blcg_ltc[] = {
382 {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000}, 380 {.addr = 0x00154030U, .prod = 0x00000044U, .disable = 0x00000000U},
383 {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000}, 381 {.addr = 0x00154040U, .prod = 0x00000044U, .disable = 0x00000000U},
384 {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000}, 382 {.addr = 0x001545e0U, .prod = 0x00000044U, .disable = 0x00000000U},
385 {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000}, 383 {.addr = 0x001545c8U, .prod = 0x00000044U, .disable = 0x00000000U},
386 {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000}, 384 {.addr = 0x001547e0U, .prod = 0x00000044U, .disable = 0x00000000U},
387 {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000}, 385 {.addr = 0x001547c8U, .prod = 0x00000044U, .disable = 0x00000000U},
388 {.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000}, 386 {.addr = 0x001549e0U, .prod = 0x00000044U, .disable = 0x00000000U},
389 {.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000}, 387 {.addr = 0x001549c8U, .prod = 0x00000044U, .disable = 0x00000000U},
390 {.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000}, 388 {.addr = 0x00154be0U, .prod = 0x00000044U, .disable = 0x00000000U},
391 {.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000}, 389 {.addr = 0x00154bc8U, .prod = 0x00000044U, .disable = 0x00000000U},
392 {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000}, 390 {.addr = 0x001543e0U, .prod = 0x00000044U, .disable = 0x00000000U},
393 {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000}, 391 {.addr = 0x001543c8U, .prod = 0x00000044U, .disable = 0x00000000U},
394 {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000}, 392 {.addr = 0x00156030U, .prod = 0x00000044U, .disable = 0x00000000U},
395 {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000}, 393 {.addr = 0x00156040U, .prod = 0x00000044U, .disable = 0x00000000U},
396 {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000}, 394 {.addr = 0x001565e0U, .prod = 0x00000044U, .disable = 0x00000000U},
397 {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000}, 395 {.addr = 0x001565c8U, .prod = 0x00000044U, .disable = 0x00000000U},
398 {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000}, 396 {.addr = 0x001567e0U, .prod = 0x00000044U, .disable = 0x00000000U},
399 {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000}, 397 {.addr = 0x001567c8U, .prod = 0x00000044U, .disable = 0x00000000U},
400 {.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000}, 398 {.addr = 0x001569e0U, .prod = 0x00000044U, .disable = 0x00000000U},
401 {.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000}, 399 {.addr = 0x001569c8U, .prod = 0x00000044U, .disable = 0x00000000U},
402 {.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000}, 400 {.addr = 0x00156be0U, .prod = 0x00000044U, .disable = 0x00000000U},
403 {.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000}, 401 {.addr = 0x00156bc8U, .prod = 0x00000044U, .disable = 0x00000000U},
404 {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000}, 402 {.addr = 0x001563e0U, .prod = 0x00000044U, .disable = 0x00000000U},
405 {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000}, 403 {.addr = 0x001563c8U, .prod = 0x00000044U, .disable = 0x00000000U},
406 /* fix priv error */ 404 /* fix priv error */
407 /*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/ 405 /*{.addr = 0x00158030U, .prod = 0x00000044U, .disable = 0x00000000U},*/
408 /*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/ 406 /*{.addr = 0x00158040U, .prod = 0x00000044U, .disable = 0x00000000U},*/
409 /*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/ 407 /*{.addr = 0x001585e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
410 /*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/ 408 /*{.addr = 0x001585c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
411 /*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/ 409 /*{.addr = 0x001587e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
412 /*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/ 410 /*{.addr = 0x001587c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
413 /*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/ 411 /*{.addr = 0x001589e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
414 /*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/ 412 /*{.addr = 0x001589c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
415 /*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/ 413 /*{.addr = 0x00158be0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
416 /*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/ 414 /*{.addr = 0x00158bc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
417 /*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/ 415 /*{.addr = 0x001583e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
418 /*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/ 416 /*{.addr = 0x001583c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
419 /*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/ 417 /*{.addr = 0x0015a030U, .prod = 0x00000044U, .disable = 0x00000000U},*/
420 /*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/ 418 /*{.addr = 0x0015a040U, .prod = 0x00000044U, .disable = 0x00000000U},*/
421 /*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/ 419 /*{.addr = 0x0015a5e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
422 /*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/ 420 /*{.addr = 0x0015a5c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
423 /*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/ 421 /*{.addr = 0x0015a7e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
424 /*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/ 422 /*{.addr = 0x0015a7c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
425 /*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/ 423 /*{.addr = 0x0015a9e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
426 /*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/ 424 /*{.addr = 0x0015a9c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
427 /*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/ 425 /*{.addr = 0x0015abe0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
428 /*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/ 426 /*{.addr = 0x0015abc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
429 /*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/ 427 /*{.addr = 0x0015a3e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
430 /*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/ 428 /*{.addr = 0x0015a3c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
431 /*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/ 429 /*{.addr = 0x0015c030U, .prod = 0x00000044U, .disable = 0x00000000U},*/
432 /*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/ 430 /*{.addr = 0x0015c040U, .prod = 0x00000044U, .disable = 0x00000000U},*/
433 /*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/ 431 /*{.addr = 0x0015c5e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
434 /*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/ 432 /*{.addr = 0x0015c5c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
435 /*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/ 433 /*{.addr = 0x0015c7e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
436 /*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/ 434 /*{.addr = 0x0015c7c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
437 /*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/ 435 /*{.addr = 0x0015c9e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
438 /*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/ 436 /*{.addr = 0x0015c9c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
439 /*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/ 437 /*{.addr = 0x0015cbe0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
440 /*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/ 438 /*{.addr = 0x0015cbc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
441 /*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/ 439 /*{.addr = 0x0015c3e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
442 /*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/ 440 /*{.addr = 0x0015c3c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
443 /*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/ 441 /*{.addr = 0x0015e030U, .prod = 0x00000044U, .disable = 0x00000000U},*/
444 /*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/ 442 /*{.addr = 0x0015e040U, .prod = 0x00000044U, .disable = 0x00000000U},*/
445 /*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/ 443 /*{.addr = 0x0015e5e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
446 /*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/ 444 /*{.addr = 0x0015e5c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
447 /*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/ 445 /*{.addr = 0x0015e7e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
448 /*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/ 446 /*{.addr = 0x0015e7c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
449 /*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/ 447 /*{.addr = 0x0015e9e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
450 /*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/ 448 /*{.addr = 0x0015e9c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
451 /*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/ 449 /*{.addr = 0x0015ebe0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
452 /*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/ 450 /*{.addr = 0x0015ebc8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
453 /*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/ 451 /*{.addr = 0x0015e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},*/
454 /*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/ 452 /*{.addr = 0x0015e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},*/
455 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, 453 {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
456 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, 454 {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
457 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, 455 {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
458 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, 456 {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
459}; 457};
460 458
461/* blcg pwr_csb */ 459/* blcg pwr_csb */
462static const struct gating_desc gv100_blcg_pwr_csb[] = { 460static const struct gating_desc gv100_blcg_pwr_csb[] = {
463 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, 461 {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U},
464}; 462};
465 463
466/* blcg pmu */ 464/* blcg pmu */
467static const struct gating_desc gv100_blcg_pmu[] = { 465static const struct gating_desc gv100_blcg_pmu[] = {
468 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, 466 {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
469}; 467};
470 468
471/* blcg Xbar */ 469/* blcg Xbar */
472static const struct gating_desc gv100_blcg_xbar[] = { 470static const struct gating_desc gv100_blcg_xbar[] = {
473 {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, 471 {.addr = 0x0013c820U, .prod = 0x0001004aU, .disable = 0x00000000U},
474 {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, 472 {.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U},
475 {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, 473 {.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U},
476 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, 474 {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
477 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, 475 {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U},
478 {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, 476 {.addr = 0x0013cc20U, .prod = 0x00000042U, .disable = 0x00000000U},
479 {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000}, 477 {.addr = 0x0013cc40U, .prod = 0x00000042U, .disable = 0x00000000U},
480 {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000}, 478 {.addr = 0x0013cc60U, .prod = 0x00000042U, .disable = 0x00000000U},
481 {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000}, 479 {.addr = 0x0013cc80U, .prod = 0x00000042U, .disable = 0x00000000U},
482 {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000}, 480 {.addr = 0x0013cca0U, .prod = 0x00000042U, .disable = 0x00000000U},
483}; 481};
484 482
485/* pg gr */ 483/* pg gr */
@@ -491,18 +489,15 @@ void gv100_slcg_bus_load_gating_prod(struct gk20a *g,
491 bool prod) 489 bool prod)
492{ 490{
493 u32 i; 491 u32 i;
494 u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc); 492 u32 size = (u32)(sizeof(gv100_slcg_bus) / GATING_DESC_SIZE);
495 493
496 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 494 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
497 return; 495 for (i = 0; i < size; i++) {
498 496 u32 reg = gv100_slcg_bus[i].addr;
499 for (i = 0; i < size; i++) { 497 u32 val = prod ? gv100_slcg_bus[i].prod :
500 if (prod) 498 gv100_slcg_bus[i].disable;
501 gk20a_writel(g, gv100_slcg_bus[i].addr, 499 gk20a_writel(g, reg, val);
502 gv100_slcg_bus[i].prod); 500 }
503 else
504 gk20a_writel(g, gv100_slcg_bus[i].addr,
505 gv100_slcg_bus[i].disable);
506 } 501 }
507} 502}
508 503
@@ -510,18 +505,15 @@ void gv100_slcg_ce2_load_gating_prod(struct gk20a *g,
510 bool prod) 505 bool prod)
511{ 506{
512 u32 i; 507 u32 i;
513 u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc); 508 u32 size = (u32)(sizeof(gv100_slcg_ce2) / GATING_DESC_SIZE);
514 509
515 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 510 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
516 return; 511 for (i = 0; i < size; i++) {
517 512 u32 reg = gv100_slcg_ce2[i].addr;
518 for (i = 0; i < size; i++) { 513 u32 val = prod ? gv100_slcg_ce2[i].prod :
519 if (prod) 514 gv100_slcg_ce2[i].disable;
520 gk20a_writel(g, gv100_slcg_ce2[i].addr, 515 gk20a_writel(g, reg, val);
521 gv100_slcg_ce2[i].prod); 516 }
522 else
523 gk20a_writel(g, gv100_slcg_ce2[i].addr,
524 gv100_slcg_ce2[i].disable);
525 } 517 }
526} 518}
527 519
@@ -529,42 +521,38 @@ void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g,
529 bool prod) 521 bool prod)
530{ 522{
531 u32 i; 523 u32 i;
532 u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc); 524 u32 size = (u32)(sizeof(gv100_slcg_chiplet) / GATING_DESC_SIZE);
533 525
534 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 526 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
535 return; 527 for (i = 0; i < size; i++) {
536 528 u32 reg = gv100_slcg_chiplet[i].addr;
537 for (i = 0; i < size; i++) { 529 u32 val = prod ? gv100_slcg_chiplet[i].prod :
538 if (prod) 530 gv100_slcg_chiplet[i].disable;
539 gk20a_writel(g, gv100_slcg_chiplet[i].addr, 531 gk20a_writel(g, reg, val);
540 gv100_slcg_chiplet[i].prod); 532 }
541 else
542 gk20a_writel(g, gv100_slcg_chiplet[i].addr,
543 gv100_slcg_chiplet[i].disable);
544 } 533 }
545} 534}
546 535
547void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, 536void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
548 bool prod) 537 bool prod)
549{ 538{
539 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
540 }
550} 541}
551 542
552void gv100_slcg_fb_load_gating_prod(struct gk20a *g, 543void gv100_slcg_fb_load_gating_prod(struct gk20a *g,
553 bool prod) 544 bool prod)
554{ 545{
555 u32 i; 546 u32 i;
556 u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc); 547 u32 size = (u32)(sizeof(gv100_slcg_fb) / GATING_DESC_SIZE);
557 548
558 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 549 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
559 return; 550 for (i = 0; i < size; i++) {
560 551 u32 reg = gv100_slcg_fb[i].addr;
561 for (i = 0; i < size; i++) { 552 u32 val = prod ? gv100_slcg_fb[i].prod :
562 if (prod) 553 gv100_slcg_fb[i].disable;
563 gk20a_writel(g, gv100_slcg_fb[i].addr, 554 gk20a_writel(g, reg, val);
564 gv100_slcg_fb[i].prod); 555 }
565 else
566 gk20a_writel(g, gv100_slcg_fb[i].addr,
567 gv100_slcg_fb[i].disable);
568 } 556 }
569} 557}
570 558
@@ -572,18 +560,15 @@ void gv100_slcg_fifo_load_gating_prod(struct gk20a *g,
572 bool prod) 560 bool prod)
573{ 561{
574 u32 i; 562 u32 i;
575 u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc); 563 u32 size = (u32)(sizeof(gv100_slcg_fifo) / GATING_DESC_SIZE);
576 564
577 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 565 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
578 return; 566 for (i = 0; i < size; i++) {
579 567 u32 reg = gv100_slcg_fifo[i].addr;
580 for (i = 0; i < size; i++) { 568 u32 val = prod ? gv100_slcg_fifo[i].prod :
581 if (prod) 569 gv100_slcg_fifo[i].disable;
582 gk20a_writel(g, gv100_slcg_fifo[i].addr, 570 gk20a_writel(g, reg, val);
583 gv100_slcg_fifo[i].prod); 571 }
584 else
585 gk20a_writel(g, gv100_slcg_fifo[i].addr,
586 gv100_slcg_fifo[i].disable);
587 } 572 }
588} 573}
589 574
@@ -591,18 +576,15 @@ void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g,
591 bool prod) 576 bool prod)
592{ 577{
593 u32 i; 578 u32 i;
594 u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc); 579 u32 size = (u32)(sizeof(gv100_slcg_gr) / GATING_DESC_SIZE);
595 580
596 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 581 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
597 return; 582 for (i = 0; i < size; i++) {
598 583 u32 reg = gv100_slcg_gr[i].addr;
599 for (i = 0; i < size; i++) { 584 u32 val = prod ? gv100_slcg_gr[i].prod :
600 if (prod) 585 gv100_slcg_gr[i].disable;
601 gk20a_writel(g, gv100_slcg_gr[i].addr, 586 gk20a_writel(g, reg, val);
602 gv100_slcg_gr[i].prod); 587 }
603 else
604 gk20a_writel(g, gv100_slcg_gr[i].addr,
605 gv100_slcg_gr[i].disable);
606 } 588 }
607} 589}
608 590
@@ -610,18 +592,15 @@ void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g,
610 bool prod) 592 bool prod)
611{ 593{
612 u32 i; 594 u32 i;
613 u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc); 595 u32 size = (u32)(sizeof(gv100_slcg_ltc) / GATING_DESC_SIZE);
614
615 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
616 return;
617 596
597 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
618 for (i = 0; i < size; i++) { 598 for (i = 0; i < size; i++) {
619 if (prod) 599 u32 reg = gv100_slcg_ltc[i].addr;
620 gk20a_writel(g, gv100_slcg_ltc[i].addr, 600 u32 val = prod ? gv100_slcg_ltc[i].prod :
621 gv100_slcg_ltc[i].prod); 601 gv100_slcg_ltc[i].disable;
622 else 602 gk20a_writel(g, reg, val);
623 gk20a_writel(g, gv100_slcg_ltc[i].addr, 603 }
624 gv100_slcg_ltc[i].disable);
625 } 604 }
626} 605}
627 606
@@ -629,18 +608,15 @@ void gv100_slcg_perf_load_gating_prod(struct gk20a *g,
629 bool prod) 608 bool prod)
630{ 609{
631 u32 i; 610 u32 i;
632 u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc); 611 u32 size = (u32)(sizeof(gv100_slcg_perf) / GATING_DESC_SIZE);
633 612
634 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 613 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
635 return; 614 for (i = 0; i < size; i++) {
636 615 u32 reg = gv100_slcg_perf[i].addr;
637 for (i = 0; i < size; i++) { 616 u32 val = prod ? gv100_slcg_perf[i].prod :
638 if (prod) 617 gv100_slcg_perf[i].disable;
639 gk20a_writel(g, gv100_slcg_perf[i].addr, 618 gk20a_writel(g, reg, val);
640 gv100_slcg_perf[i].prod); 619 }
641 else
642 gk20a_writel(g, gv100_slcg_perf[i].addr,
643 gv100_slcg_perf[i].disable);
644 } 620 }
645} 621}
646 622
@@ -648,18 +624,15 @@ void gv100_slcg_priring_load_gating_prod(struct gk20a *g,
648 bool prod) 624 bool prod)
649{ 625{
650 u32 i; 626 u32 i;
651 u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc); 627 u32 size = (u32)(sizeof(gv100_slcg_priring) / GATING_DESC_SIZE);
652 628
653 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 629 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
654 return; 630 for (i = 0; i < size; i++) {
655 631 u32 reg = gv100_slcg_priring[i].addr;
656 for (i = 0; i < size; i++) { 632 u32 val = prod ? gv100_slcg_priring[i].prod :
657 if (prod) 633 gv100_slcg_priring[i].disable;
658 gk20a_writel(g, gv100_slcg_priring[i].addr, 634 gk20a_writel(g, reg, val);
659 gv100_slcg_priring[i].prod); 635 }
660 else
661 gk20a_writel(g, gv100_slcg_priring[i].addr,
662 gv100_slcg_priring[i].disable);
663 } 636 }
664} 637}
665 638
@@ -667,18 +640,15 @@ void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
667 bool prod) 640 bool prod)
668{ 641{
669 u32 i; 642 u32 i;
670 u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc); 643 u32 size = (u32)(sizeof(gv100_slcg_pwr_csb) / GATING_DESC_SIZE);
671 644
672 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 645 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
673 return; 646 for (i = 0; i < size; i++) {
674 647 u32 reg = gv100_slcg_pwr_csb[i].addr;
675 for (i = 0; i < size; i++) { 648 u32 val = prod ? gv100_slcg_pwr_csb[i].prod :
676 if (prod) 649 gv100_slcg_pwr_csb[i].disable;
677 gk20a_writel(g, gv100_slcg_pwr_csb[i].addr, 650 gk20a_writel(g, reg, val);
678 gv100_slcg_pwr_csb[i].prod); 651 }
679 else
680 gk20a_writel(g, gv100_slcg_pwr_csb[i].addr,
681 gv100_slcg_pwr_csb[i].disable);
682 } 652 }
683} 653}
684 654
@@ -686,18 +656,15 @@ void gv100_slcg_pmu_load_gating_prod(struct gk20a *g,
686 bool prod) 656 bool prod)
687{ 657{
688 u32 i; 658 u32 i;
689 u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc); 659 u32 size = (u32)(sizeof(gv100_slcg_pmu) / GATING_DESC_SIZE);
690 660
691 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 661 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
692 return; 662 for (i = 0; i < size; i++) {
693 663 u32 reg = gv100_slcg_pmu[i].addr;
694 for (i = 0; i < size; i++) { 664 u32 val = prod ? gv100_slcg_pmu[i].prod :
695 if (prod) 665 gv100_slcg_pmu[i].disable;
696 gk20a_writel(g, gv100_slcg_pmu[i].addr, 666 gk20a_writel(g, reg, val);
697 gv100_slcg_pmu[i].prod); 667 }
698 else
699 gk20a_writel(g, gv100_slcg_pmu[i].addr,
700 gv100_slcg_pmu[i].disable);
701 } 668 }
702} 669}
703 670
@@ -705,18 +672,15 @@ void gv100_slcg_therm_load_gating_prod(struct gk20a *g,
705 bool prod) 672 bool prod)
706{ 673{
707 u32 i; 674 u32 i;
708 u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc); 675 u32 size = (u32)(sizeof(gv100_slcg_therm) / GATING_DESC_SIZE);
709 676
710 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 677 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
711 return; 678 for (i = 0; i < size; i++) {
712 679 u32 reg = gv100_slcg_therm[i].addr;
713 for (i = 0; i < size; i++) { 680 u32 val = prod ? gv100_slcg_therm[i].prod :
714 if (prod) 681 gv100_slcg_therm[i].disable;
715 gk20a_writel(g, gv100_slcg_therm[i].addr, 682 gk20a_writel(g, reg, val);
716 gv100_slcg_therm[i].prod); 683 }
717 else
718 gk20a_writel(g, gv100_slcg_therm[i].addr,
719 gv100_slcg_therm[i].disable);
720 } 684 }
721} 685}
722 686
@@ -724,18 +688,15 @@ void gv100_slcg_xbar_load_gating_prod(struct gk20a *g,
724 bool prod) 688 bool prod)
725{ 689{
726 u32 i; 690 u32 i;
727 u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc); 691 u32 size = (u32)(sizeof(gv100_slcg_xbar) / GATING_DESC_SIZE);
728 692
729 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 693 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
730 return; 694 for (i = 0; i < size; i++) {
731 695 u32 reg = gv100_slcg_xbar[i].addr;
732 for (i = 0; i < size; i++) { 696 u32 val = prod ? gv100_slcg_xbar[i].prod :
733 if (prod) 697 gv100_slcg_xbar[i].disable;
734 gk20a_writel(g, gv100_slcg_xbar[i].addr, 698 gk20a_writel(g, reg, val);
735 gv100_slcg_xbar[i].prod); 699 }
736 else
737 gk20a_writel(g, gv100_slcg_xbar[i].addr,
738 gv100_slcg_xbar[i].disable);
739 } 700 }
740} 701}
741 702
@@ -743,18 +704,15 @@ void gv100_blcg_bus_load_gating_prod(struct gk20a *g,
743 bool prod) 704 bool prod)
744{ 705{
745 u32 i; 706 u32 i;
746 u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc); 707 u32 size = (u32)(sizeof(gv100_blcg_bus) / GATING_DESC_SIZE);
747 708
748 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 709 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
749 return; 710 for (i = 0; i < size; i++) {
750 711 u32 reg = gv100_blcg_bus[i].addr;
751 for (i = 0; i < size; i++) { 712 u32 val = prod ? gv100_blcg_bus[i].prod :
752 if (prod) 713 gv100_blcg_bus[i].disable;
753 gk20a_writel(g, gv100_blcg_bus[i].addr, 714 gk20a_writel(g, reg, val);
754 gv100_blcg_bus[i].prod); 715 }
755 else
756 gk20a_writel(g, gv100_blcg_bus[i].addr,
757 gv100_blcg_bus[i].disable);
758 } 716 }
759} 717}
760 718
@@ -762,18 +720,15 @@ void gv100_blcg_ce_load_gating_prod(struct gk20a *g,
762 bool prod) 720 bool prod)
763{ 721{
764 u32 i; 722 u32 i;
765 u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc); 723 u32 size = (u32)(sizeof(gv100_blcg_ce) / GATING_DESC_SIZE);
766 724
767 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 725 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
768 return; 726 for (i = 0; i < size; i++) {
769 727 u32 reg = gv100_blcg_ce[i].addr;
770 for (i = 0; i < size; i++) { 728 u32 val = prod ? gv100_blcg_ce[i].prod :
771 if (prod) 729 gv100_blcg_ce[i].disable;
772 gk20a_writel(g, gv100_blcg_ce[i].addr, 730 gk20a_writel(g, reg, val);
773 gv100_blcg_ce[i].prod); 731 }
774 else
775 gk20a_writel(g, gv100_blcg_ce[i].addr,
776 gv100_blcg_ce[i].disable);
777 } 732 }
778} 733}
779 734
@@ -781,18 +736,15 @@ void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
781 bool prod) 736 bool prod)
782{ 737{
783 u32 i; 738 u32 i;
784 u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc); 739 u32 size = (u32)(sizeof(gv100_blcg_ctxsw_prog) / GATING_DESC_SIZE);
785 740
786 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 741 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
787 return; 742 for (i = 0; i < size; i++) {
788 743 u32 reg = gv100_blcg_ctxsw_prog[i].addr;
789 for (i = 0; i < size; i++) { 744 u32 val = prod ? gv100_blcg_ctxsw_prog[i].prod :
790 if (prod) 745 gv100_blcg_ctxsw_prog[i].disable;
791 gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr, 746 gk20a_writel(g, reg, val);
792 gv100_blcg_ctxsw_prog[i].prod); 747 }
793 else
794 gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr,
795 gv100_blcg_ctxsw_prog[i].disable);
796 } 748 }
797} 749}
798 750
@@ -800,18 +752,15 @@ void gv100_blcg_fb_load_gating_prod(struct gk20a *g,
800 bool prod) 752 bool prod)
801{ 753{
802 u32 i; 754 u32 i;
803 u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc); 755 u32 size = (u32)(sizeof(gv100_blcg_fb) / GATING_DESC_SIZE);
804 756
805 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 757 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
806 return; 758 for (i = 0; i < size; i++) {
807 759 u32 reg = gv100_blcg_fb[i].addr;
808 for (i = 0; i < size; i++) { 760 u32 val = prod ? gv100_blcg_fb[i].prod :
809 if (prod) 761 gv100_blcg_fb[i].disable;
810 gk20a_writel(g, gv100_blcg_fb[i].addr, 762 gk20a_writel(g, reg, val);
811 gv100_blcg_fb[i].prod); 763 }
812 else
813 gk20a_writel(g, gv100_blcg_fb[i].addr,
814 gv100_blcg_fb[i].disable);
815 } 764 }
816} 765}
817 766
@@ -819,18 +768,15 @@ void gv100_blcg_fifo_load_gating_prod(struct gk20a *g,
819 bool prod) 768 bool prod)
820{ 769{
821 u32 i; 770 u32 i;
822 u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc); 771 u32 size = (u32)(sizeof(gv100_blcg_fifo) / GATING_DESC_SIZE);
823
824 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
825 return;
826 772
773 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
827 for (i = 0; i < size; i++) { 774 for (i = 0; i < size; i++) {
828 if (prod) 775 u32 reg = gv100_blcg_fifo[i].addr;
829 gk20a_writel(g, gv100_blcg_fifo[i].addr, 776 u32 val = prod ? gv100_blcg_fifo[i].prod :
830 gv100_blcg_fifo[i].prod); 777 gv100_blcg_fifo[i].disable;
831 else 778 gk20a_writel(g, reg, val);
832 gk20a_writel(g, gv100_blcg_fifo[i].addr, 779 }
833 gv100_blcg_fifo[i].disable);
834 } 780 }
835} 781}
836 782
@@ -838,18 +784,15 @@ void gv100_blcg_gr_load_gating_prod(struct gk20a *g,
838 bool prod) 784 bool prod)
839{ 785{
840 u32 i; 786 u32 i;
841 u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc); 787 u32 size = (u32)(sizeof(gv100_blcg_gr) / GATING_DESC_SIZE);
842 788
843 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 789 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
844 return; 790 for (i = 0; i < size; i++) {
845 791 u32 reg = gv100_blcg_gr[i].addr;
846 for (i = 0; i < size; i++) { 792 u32 val = prod ? gv100_blcg_gr[i].prod :
847 if (prod) 793 gv100_blcg_gr[i].disable;
848 gk20a_writel(g, gv100_blcg_gr[i].addr, 794 gk20a_writel(g, reg, val);
849 gv100_blcg_gr[i].prod); 795 }
850 else
851 gk20a_writel(g, gv100_blcg_gr[i].addr,
852 gv100_blcg_gr[i].disable);
853 } 796 }
854} 797}
855 798
@@ -857,18 +800,15 @@ void gv100_blcg_ltc_load_gating_prod(struct gk20a *g,
857 bool prod) 800 bool prod)
858{ 801{
859 u32 i; 802 u32 i;
860 u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc); 803 u32 size = (u32)(sizeof(gv100_blcg_ltc) / GATING_DESC_SIZE);
861 804
862 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 805 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
863 return; 806 for (i = 0; i < size; i++) {
864 807 u32 reg = gv100_blcg_ltc[i].addr;
865 for (i = 0; i < size; i++) { 808 u32 val = prod ? gv100_blcg_ltc[i].prod :
866 if (prod) 809 gv100_blcg_ltc[i].disable;
867 gk20a_writel(g, gv100_blcg_ltc[i].addr, 810 gk20a_writel(g, reg, val);
868 gv100_blcg_ltc[i].prod); 811 }
869 else
870 gk20a_writel(g, gv100_blcg_ltc[i].addr,
871 gv100_blcg_ltc[i].disable);
872 } 812 }
873} 813}
874 814
@@ -876,18 +816,15 @@ void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
876 bool prod) 816 bool prod)
877{ 817{
878 u32 i; 818 u32 i;
879 u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc); 819 u32 size = (u32)(sizeof(gv100_blcg_pwr_csb) / GATING_DESC_SIZE);
880 820
881 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 821 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
882 return; 822 for (i = 0; i < size; i++) {
883 823 u32 reg = gv100_blcg_pwr_csb[i].addr;
884 for (i = 0; i < size; i++) { 824 u32 val = prod ? gv100_blcg_pwr_csb[i].prod :
885 if (prod) 825 gv100_blcg_pwr_csb[i].disable;
886 gk20a_writel(g, gv100_blcg_pwr_csb[i].addr, 826 gk20a_writel(g, reg, val);
887 gv100_blcg_pwr_csb[i].prod); 827 }
888 else
889 gk20a_writel(g, gv100_blcg_pwr_csb[i].addr,
890 gv100_blcg_pwr_csb[i].disable);
891 } 828 }
892} 829}
893 830
@@ -895,18 +832,15 @@ void gv100_blcg_pmu_load_gating_prod(struct gk20a *g,
895 bool prod) 832 bool prod)
896{ 833{
897 u32 i; 834 u32 i;
898 u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc); 835 u32 size = (u32)(sizeof(gv100_blcg_pmu) / GATING_DESC_SIZE);
899 836
900 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 837 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
901 return; 838 for (i = 0; i < size; i++) {
902 839 u32 reg = gv100_blcg_pmu[i].addr;
903 for (i = 0; i < size; i++) { 840 u32 val = prod ? gv100_blcg_pmu[i].prod :
904 if (prod) 841 gv100_blcg_pmu[i].disable;
905 gk20a_writel(g, gv100_blcg_pmu[i].addr, 842 gk20a_writel(g, reg, val);
906 gv100_blcg_pmu[i].prod); 843 }
907 else
908 gk20a_writel(g, gv100_blcg_pmu[i].addr,
909 gv100_blcg_pmu[i].disable);
910 } 844 }
911} 845}
912 846
@@ -914,18 +848,15 @@ void gv100_blcg_xbar_load_gating_prod(struct gk20a *g,
914 bool prod) 848 bool prod)
915{ 849{
916 u32 i; 850 u32 i;
917 u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc); 851 u32 size = (u32)(sizeof(gv100_blcg_xbar) / GATING_DESC_SIZE);
918 852
919 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 853 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
920 return; 854 for (i = 0; i < size; i++) {
921 855 u32 reg = gv100_blcg_xbar[i].addr;
922 for (i = 0; i < size; i++) { 856 u32 val = prod ? gv100_blcg_xbar[i].prod :
923 if (prod) 857 gv100_blcg_xbar[i].disable;
924 gk20a_writel(g, gv100_blcg_xbar[i].addr, 858 gk20a_writel(g, reg, val);
925 gv100_blcg_xbar[i].prod); 859 }
926 else
927 gk20a_writel(g, gv100_blcg_xbar[i].addr,
928 gv100_blcg_xbar[i].disable);
929 } 860 }
930} 861}
931 862
@@ -933,19 +864,14 @@ void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g,
933 bool prod) 864 bool prod)
934{ 865{
935 u32 i; 866 u32 i;
936 u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc); 867 u32 size = (u32)(sizeof(gv100_pg_gr) / GATING_DESC_SIZE);
937 868
938 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 869 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
939 return; 870 for (i = 0; i < size; i++) {
940 871 u32 reg = gv100_pg_gr[i].addr;
941 for (i = 0; i < size; i++) { 872 u32 val = prod ? gv100_pg_gr[i].prod :
942 if (prod) 873 gv100_pg_gr[i].disable;
943 gk20a_writel(g, gv100_pg_gr[i].addr, 874 gk20a_writel(g, reg, val);
944 gv100_pg_gr[i].prod); 875 }
945 else
946 gk20a_writel(g, gv100_pg_gr[i].addr,
947 gv100_pg_gr[i].disable);
948 } 876 }
949} 877}
950
951#endif /* __gv100_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:37:30 -0400